The high-performance Cortex-M4 processor provides a low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.
- The Cortex-M4 core has low-latency interrupt processing with the following features:
- A 32-bit Arm®Thumb® instruction set optimized for embedded applications
- Handler and thread modes
- Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit
- Support for ARMv6 unaligned accesses
- Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low-latency interrupt processing. The NVIC includes the following features:
- Bits of priority configurable from 3 to 8
- Dynamic reprioritization of interrupts
- Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels
- Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts
- Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction overhead
- Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support
- Bus interfaces:
- Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces
- Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations
- Low-cost debug solution featuring:
- Debug access to all memory and registers in the system, including access to memory-mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted
- Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access
- Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches