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ZHCSOT4B February 2020 – May 2021 CC3230S , CC3230SF

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8.16.6.4.1 I²C Timing Parameters⁽³⁾

PARAMETER NUMBER			MIN	MAX	UNIT
T2	t_LP	Clock low period	See ⁽¹⁾		System clock
T3	t_SRT	SCL/SDA rise time		See ⁽²⁾	ns
T4	t_DH	Data hold time	N/A
T5	t_SFT	SCL/SDA fall time	3		ns
T6	t_HT	Clock high time	See ⁽¹⁾		System clock
T7	t_DS	Data setup time	tLP/2		System clock
T8	t_SCSR	Start condition setup time	36		System clock
T9	t_SCS	Stop condition setup time	24		System clock

(1) This value depends on the value programmed in the clock period register of I²C. Maximum output frequency is the result of the minimal value programmed in this register.

(2) Because I²C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of an external pullup resistor. Rise time depends on the value of the external signal capacitance and external pullup register.

(3) All timing is with 6-mA drive and 20-pF load.

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机械数据 (封装 | 引脚)

散热焊盘机械数据 (封装 | 引脚)

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8.16.6.4.1 I2C Timing Parameters(3)

8.16.6.4.1 I²C Timing Parameters⁽³⁾