ZHCSJC1D April 2019 – May 2021 CC3235S , CC3235SF
PRODUCTION DATA
Table 7-5 describes the use, drive strength, and default state of analog and digital multiplexed pins at first-time power up and reset (nRESET pulled low).
| Pin | Board-Level Configuration and Use | Default State at First Power Up or Forced Reset | State After Configuration of Analog Switches (ACTIVE, LPDS, and HIB Power Modes) | Maximum Effective Drive Strength (mA) |
|---|---|---|---|---|
| 45 | VDD_ANA2 (pin 47) must be shorted to the input supply rail. Otherwise, the pin is driven by the ANA2 DC/DC. | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 50 | Generic I/O | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 52 | The pin must have an external pullup of 100 kΩ to the supply rail and must be used in output signals only. | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 53 | Generic I/O | Analog is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 57 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 58 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 59 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |
| 60 | Analog signal (1.8-V absolute, 1.46-V full scale) | ADC is isolated. The digital I/O cell is also isolated. | Determined by the I/O state, as are other digital I/Os. | 4 |