米6体育平台手机版

ZHCSJC1E April 2019 – December 2024 CC3235S , CC3235SF

PRODUCTION DATA

1
1 特性
2 应用
3 说明
4 功能方框图
5 Device Comparison
1. 5.1 Related Products
6 Pin Configuration and Functions
7 Specifications
1. 7.1 Absolute Maximum Ratings
2. 7.2 ESD Ratings
3. 7.3 Power-On Hours (POH)
4. 7.4 Recommended Operating Conditions
5. 7.5 Current Consumption Summary (CC3235S)
  1. 24
  2. 25
6. 7.6 Current Consumption Summary (CC3235SF)
  1. 27
  2. 28
7. 7.7 TX Power Control for 2.4 GHz Band
8. 7.8 TX Power Control for 5 GHz
9. 7.9 Brownout and Blackout Conditions
10. 7.10 Electrical Characteristics for GPIO Pins
  1. 33
  2. 34
11. 7.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
12. 7.12 WLAN Receiver Characteristics
  1. 37
  2. 38
13. 7.13 WLAN Transmitter Characteristics
  1. 40
  2. 41
14. 7.14 WLAN Transmitter Out-of-Band Emissions
  1. 43
  2. 44
15. 7.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
16. 7.16 Thermal Resistance Characteristics for RGK Package
17. 7.17 Timing and Switching Characteristics
  1. 7.17.1 Power Supply Sequencing
  2. 7.17.2 Device Reset
  3. 7.17.3 Reset Timing
    1. 7.17.3.1 nRESET (32kHz Crystal)
    2. 52
    3. 53
    4. 7.17.3.2 nRESET (External 32kHz Clock)
      1. 55
  4. 7.17.4 Wakeup From HIBERNATE Mode
  5. 7.17.5 Clock Specifications
  6. 7.17.6 Peripherals Timing
    1. 7.17.6.1 SPI
      1. 7.17.6.1.1 SPI Master
        
        68
      2. 7.17.6.1.2 SPI Slave
        
        70
    2. 7.17.6.2 I2S
      1. 7.17.6.2.1 I2S Transmit Mode
        
        73
      2. 7.17.6.2.2 I2S Receive Mode
        
        75
    3. 7.17.6.3 GPIOs
      1. 7.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3V)
        
        78
      2. 7.17.6.3.2 GPIO Input Transition Time Parameters
        
        80
    4. 7.17.6.4 I2C
      1. 82
    5. 7.17.6.5 IEEE 1149.1 JTAG
      1. 84
    6. 7.17.6.6 ADC
      1. 86
    7. 7.17.6.7 Camera Parallel Port
      1. 88
    8. 7.17.6.8 UART
    9. 7.17.6.9 SD Host
    10. 7.17.6.10 Timers
8 Detailed Description
9 Applications, Implementation, and Layout
1. 9.1 Application Information
2. 9.2 PCB Layout Guidelines
10Device and Documentation Support
11Revision History
12Mechanical, Packaging, and Orderable Information
1. 12.1 Packaging Information
  1. 12.1.1 Packaging Option Addendum

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Table 7-28 I²C Timing Parameters⁽¹⁾

PARAMETER NUMBER			MIN	MAX	UNIT
T2	t_LP	Clock low period	See ⁽²⁾		System clock
T3	t_SRT	SCL/SDA rise time		See ⁽³⁾	ns
T4	t_DH	Data hold time	N/A
T5	t_SFT	SCL/SDA fall time	3		ns
T6	t_HT	Clock high time	See ⁽²⁾		System clock
T7	t_DS	Data setup time	tLP/2		System clock
T8	t_SCSR	Start condition setup time	36		System clock
T9	t_SCS	Stop condition setup time	24		System clock

(1) All timing is with a 6mA drive and 20pF load.

(2) This value depends on the value programmed in the clock period register of I²C. Maximum output frequency is the result of the minimal value programmed in this register.

(3) Because I²C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of an external pullup resistor. Rise time depends on the value of the external signal capacitance and external pullup register.

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