ZHCSJC1D April 2019 – May 2021 CC3235S , CC3235SF
PRODUCTION DATA
From a power-management perspective, the CC3235x device comprises the following two independent subsystems:
Each subsystem operates in one of several power states.
The Arm® Cortex®-M4 application processor runs the user application loaded from an external serial flash, or internal flash (in CC3235SF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer functions.
The user program controls the power state of the application processor subsystem. The application processor can be in one of the five modes described in Table 9-2.
| APPLICATION PROCESSOR (MCU) MODE(1) | DESCRIPTION |
|---|---|
| MCU active mode | MCU executing code at a state rate of 80 MHz |
| MCU sleep mode | The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity from any GPIO line or peripheral. |
| MCU LPDS mode | State information is lost and only certain MCU-specific register configurations are retained. The MCU can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.) Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the wake-up source. |
| MCU hibernate mode | The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly powered by the input supply is retained. The RTC continues running and the MCU supports wakeup from an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15 ms plus the time to load the application from serial flash, which varies according to code size. In this mode, the MCU can be configured to wake up using the RTC timer or external event on a GPIO. |
| MCU shutdown mode | The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the nRESET line is changed (low to shut down, high to turn on). |
The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network activity, the NWP sleeps most of the time and wakes up only for beacon reception (see
Table 9-3).
| NETWORK PROCESSOR MODE | DESCRIPTION |
|---|---|
| Network active mode (processing layer 3, 2, and 1) | Transmitting or receiving IP protocol packets |
| Network active mode (processing layer 2 and 1) | Transmitting or receiving MAC management frames; IP processing is not required |
| Network active listen mode | Special power-optimized active mode for receiving beacon frames (no other frames are supported) |
| Network connected Idle | A composite mode that implements 802.11 infrastructure power-save operation. The CC3235x NWP automatically enters LPDS mode between beacons and then wakes into active listen mode to receive a beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS mode and the cycle repeats. |
| Advanced features of long sleep interval and IoT low power for extending LPDS time for up to 22 seconds while maintaining Wi-Fi connection is supported in this mode. | |
| Network LPDS mode | Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake up |
| Network disabled | The network is disabled |
The operation of the application and network processor ensures that the device remains in the lowest power mode most of the time to preserve battery life.
The following examples show the use of the power modes in applications: