米6体育平台手机版

ZHCSJC1D April 2019 – May 2021 CC3235S , CC3235SF

PRODUCTION DATA

1 特性
2 应用
3 说明
4 功能方框图
5 Revision History
6 Device Comparison
1. 6.1 Related Products
7 Terminal Configuration and Functions
8 Specifications
1. 8.1 Absolute Maximum Ratings
2. 8.2 ESD Ratings
3. 8.3 Power-On Hours (POH)
4. 8.4 Recommended Operating Conditions
5. 8.5 Current Consumption Summary (CC3235S)
  1. 24
  2. 25
6. 8.6 Current Consumption Summary (CC3235SF)
  1. 27
  2. 28
7. 8.7 TX Power Control for 2.4 GHz Band
8. 8.8 TX Power Control for 5 GHz
9. 8.9 Brownout and Blackout Conditions
10. 8.10 Electrical Characteristics for GPIO Pins
  1. 33
  2. 34
11. 8.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
12. 8.12 WLAN Receiver Characteristics
  1. 37
  2. 38
13. 8.13 WLAN Transmitter Characteristics
  1. 40
  2. 41
14. 8.14 WLAN Transmitter Out-of-Band Emissions
  1. 43
  2. 44
15. 8.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
16. 8.16 Thermal Resistance Characteristics for RGK Package
17. 8.17 Timing and Switching Characteristics
  1. 8.17.1 Power Supply Sequencing
  2. 8.17.2 Device Reset
  3. 8.17.3 Reset Timing
    1. 8.17.3.1 nRESET (32-kHz Crystal)
    2. 52
    3. 53
    4. 8.17.3.2 nRESET (External 32-kHz Clock)
      1. 55
  4. 8.17.4 Wakeup From HIBERNATE Mode
  5. 8.17.5 Clock Specifications
  6. 8.17.6 Peripherals Timing
    1. 8.17.6.1 SPI
      1. 8.17.6.1.1 SPI Master
        
        68
      2. 8.17.6.1.2 SPI Slave
        
        70
    2. 8.17.6.2 I2S
      1. 8.17.6.2.1 I2S Transmit Mode
        
        73
      2. 8.17.6.2.2 I2S Receive Mode
        
        75
    3. 8.17.6.3 GPIOs
      1. 8.17.6.3.1 GPIO Output Transition Time Parameters (Vsupply = 3.3 V)
        
        78
      2. 8.17.6.3.2 GPIO Input Transition Time Parameters
        
        80
    4. 8.17.6.4 I2C
      1. 82
    5. 8.17.6.5 IEEE 1149.1 JTAG
      1. 84
    6. 8.17.6.6 ADC
      1. 86
    7. 8.17.6.7 Camera Parallel Port
      1. 88
    8. 8.17.6.8 UART
    9. 8.17.6.9 SD Host
    10. 8.17.6.10 Timers
9 Detailed Description
10Applications, Implementation, and Layout
1. 10.1 Application Information
2. 10.2 PCB Layout Guidelines
11Device and Documentation Support
12Mechanical, Packaging, and Orderable Information
1. 12.1 Packaging Information
  1. 12.1.1 Package Option Addendum
    1. 12.1.1.1 Packaging Information
    2. 12.1.1.2 Tape and Reel Information

封装选项

7.4 Pin Multiplexing

Table 7-4 Pin Multiplexing

Register Address	Register Name	Pin	ANALOG OR SPECIAL FUNCTION				Digital Function (XXX Field Encoding)⁽¹⁾
			JTAG	Hostless Mode	BLE COEX		0	1	2	3	4	5	6	7	8	9	10	11	12	13
			JTAG	Hostless Mode	CC_COEX_SW_OUT	CC_COEX_BLE_IN	0	1	2	3	4	5	6	7	8	9	10	11	12	13
0x4402 E0C8	GPIO_PAD_ CONFIG_10	1	—	Y	Y	Y	GPIO10	I2C_ SCL	—	GT_ PWM06	—	—	SDCARD_ CLK	UART1_ TX	—	—	—	—	GT_ CCP01	—
0x4402 E0CC	GPIO_PAD_ CONFIG_11	2	—	Y⁽²⁾	Y	—	GPIO11	I2C_ SDA	—	GT_ PWM07	pXCLK (XVCLK)	—	SDCARD_ CMD	UART1_ RX	—	—	—	—	GT_ CCP02	MCAFSX
0x4402 E0D0	GPIO_PAD_ CONFIG_12	3	—	Y	Y	Y	GPIO12	—	—	McACLK	pVS (VSYNC)	I2C_ SCL	—	UART0_ TX	—	—	—	—	GT_ CCP03	—
0x4402 E0D4	GPIO_PAD_ CONFIG_13	4	—	Y	Y	Y	GPIO13	—	—	—	pHS (HSYNC)	I2C_ SDA	—	UART0_ RX	—	—	—	—	GT_ CCP04	—
0x4402 E0D8	GPIO_PAD_ CONFIG_14	5	—	Y	Y	Y	GPIO14	—	—	—	pDATA8 (CAM_D4)	I2C_ SCL	—	GSPI_ CLK	—	—	—	—	GT_ CCP05	—
0x4402 E0DC	GPIO_PAD_ CONFIG_15	6	—	Y	Y	Y	GPIO15	—	—	—	pDATA9 (CAM_D5)	I2C_ SDA	—	GSPI_ MISO	SDCARD_ DATA0	—	—	—	—	GT_ CCP06
0x4402 E0E0	GPIO_PAD_ CONFIG_16	7	—	Y	Y	Y	GPIO16	—	—	—	pDATA10 (CAM_D6)	UART1_ TX	—	GSPI_ MOSI	SDCARD_ CLK	—	—	—	—	GT_ CCP07
0x4402 E0E4	GPIO_PAD_ CONFIG_17	8	—	Y⁽²⁾	Y	—	GPIO17	—	—	—	pDATA11 (CAM_D7)	UART1_ RX	—	GSPI_ CS	SDCARD_ CMD	—	—	—	—	—
0x4402 E0F8	GPIO_PAD_ CONFIG_22	15	—	Y	Y	Y	GPIO22	—	—	—	—	GT_ CCP04	—	McAFSX	—	—	—	—	—	—
0x4402 E0FC	GPIO_PAD_ CONFIG_23	16	Muxed with JTAG	—	—	—	GPIO23	TDI	UART1_ TX	—	—	—	—	—	—	I2C_ SCL	—	—	—	—
0x4402 E100	GPIO_PAD_ CONFIG_24	17	Muxed with JTAG TDO	—	—	—	GPIO24	TDO	UART1_ RX	—	GT_ CCP06	PWM0	McAFSX	—	—	I2C_ SDA	—	—	—	—
0x4402 E140	GPIO_PAD_ CONFIG_40	18	—	Y⁽³⁾	Y⁽³⁾	Y⁽³⁾	GPIO28	—	—	—	—	—	—	—	—	—	—	—	—	—
0x4402 E110	GPIO_PAD_ CONFIG_28	19	Muxed with JTAG or SWD and TCK	—	—	—	—	TCK	—	—	—	—	—	—	GT_ PWM03	—	—	—	—	—
0x4402 E114	GPIO_PAD_ CONFIG_29	20	Muxed with JTAG or SWD and TMSC	—	—	—	GPIO29	TMS	—	—	—	—	—	—	—	—	—	—	—	—
0x4402 E104	GPIO_PAD_ CONFIG_25	21⁽⁴⁾	—	Y⁽²⁾	Y	—	GPIO25	—	McAFSX	—	—	—	—	—	—	GT_ PWM02	—	—	—	—
0x4402 E11C	GPIO_PAD_ CONFIG_31	45⁽³⁾⁽⁵⁾	—	Y	Y	Y	GPIO31	—	UART1_ RX	—	—	—	McAXR0	GSPI_ CLK	—	UART0_ RX	—	—	McAFSX	—
0x4402 E0A0	GPIO_PAD_ CONFIG_0	50	—	Y	Y	Y	GPIO0	—	—	UART0_ RTS	McAXR0	—	McAXR1	GT_ CCP00	—	GSPI_ CS	UART1_ RTS	—	UART0_ CTS	—
0x4402 E120	GPIO_PAD_ CONFIG_32	52	—	Y⁽³⁾	Y⁽³⁾	Y⁽³⁾	GPIO32	—	McACLK	—	McAXR0	—	UART0_ RTS	—	GSPI_ MOSI	—	—	—	—	—
0x4402 E118	GPIO_PAD_ CONFIG_30	53	-—	Y⁽³⁾	Y⁽³⁾	Y⁽³⁾	GPIO30	—	McACLK	McAFSX	GT_ CCP05	—	—	GSPI_ MISO	—	UART0_ TX	—	—	—	—
0x4402 E0A4	GPIO_PAD_ CONFIG_1	55	—	—	—	—	GPIO1	—	—	UART0_ TX	pCLK (PIXCLK)	—	UART1_ TX	GT_ CCP01	—	—	—	—	—	—
0x4402 E0A8	GPIO_PAD_ CONFIG_2	57	—	—	—	—	GPIO2	—	—	UART0_ RX	—	—	UART1_ RX	GT_ CCP02	—	—	—	—	—	—
0x4402 E0AC	GPIO_PAD_ CONFIG_3	58	—	Y⁽²⁾	Y	—	GPIO3	—	—	—	pDATA7 (CAM_D3)	—	UART1_ TX	—	—	—	—	—	—	—
0x4402 E0B0	GPIO_PAD_ CONFIG_4	59	—	Y⁽²⁾	Y	—	GPIO4	—	—	—	pDATA6 (CAM_D2)	—	UART1_ RX	—	—	—	—	—	—	—
0x4402 E0B4	GPIO_PAD_ CONFIG_5	60	—	Y	Y	Y	GPIO5	—	—	—	pDATA5 (CAM_D1)	—	McAXR1	GT_ CCP05	—	—	—	—	—	—
0x4402 E0B8	GPIO_PAD_ CONFIG_6	61	—	Y	Y	Y	GPIO6	—	—	UART1_ CTS	pDATA4 (CAM_D0)	UART0_ RTS	UART0_ CTS	GT_ CCP06	—	—	—	—	—	—
0x4402 E0BC	GPIO_PAD_ CONFIG_7	62	—	—	—	—	GPIO7	—	—	UART1_ RTS	—	—	—	—	—	—	UART0_ RTS	UART0_ TX	—	McACLKX
0x4402 E0C0	GPIO_PAD_ CONFIG_8	63	—	Y	Y	Y	GPIO8	—	—	—	—	—	SDCARD_ IRQ	McAFSX	—	—	—	—	GT_ CCP06	—
0x4402 E0C4	GPIO_PAD_ CONFIG_9	64	-—	Y	Y	Y	GPIO9	—	—	GT_ PWM05	—	—	SDCARD_ DATA0	McAXR0	—	—	—	—	GT_ CCP00	—

(1) Pin mux encodings with (RD) denote the default encoding after reset release.

(2) Output Only

(3) LPDS retention unavailable.

(4) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only.

(5) Pin 45 is used by an internal DC/DC (ANA2_DCDC). For CC3235S device, pin 45 can be used as GPIO_31 if a supply is provided on pin 47.

封装选项

机械数据 (封装 | 引脚)

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.4 Pin Multiplexing