6.1 Sub-1 GHz Radio

The implemented sub-1 GHz radio module is based on the industry-leading CC1101, requiring very few external components. Figure 6-1 shows a high-level block diagram of the implemented radio.

Figure 6-1 Sub-1 GHz Radio Block Diagram

The radio features a low-IF receiver. The received RF signal is amplified by a low-noise amplifier (LNA) and down-converted in quadrature to the intermediate frequency (IF). At IF, the I/Q signals are digitized. Automatic gain control (AGC), fine channel filtering, demodulation bit, and packet synchronization are performed digitally.

The transmitter part is based on direct synthesis of the RF. The frequency synthesizer includes a completely on-chip LC VCO and a 90° phase shifter for generating the I and Q LO signals to the down-conversion mixers in receive mode.

The 26-MHz crystal oscillator generates the reference frequency for the synthesizer, as well as clocks for the ADC and the digital part.

A memory mapped register interface is used for data access, configuration, and status request by the CPU.

The digital baseband includes support for channel configuration, packet handling, and data buffering.

For complete module descriptions, see the CC430 Family User's Guide.