ZHCSQO2M August 1998 – November 2024 CD4051B , CD4052B , CD4053B
PRODUCTION DATA
6 Parameter Measurement Information
Figure 6-1 Typical
Bias VoltagesNote:
The ADDRESS (digital-control
inputs) and INHIBIT logic levels are: 0 = VSS
and 1 = VDD. The analog signal
(through the TG) may swing from VEE to VDD.
Figure 6-2 Waveforms, Channel Being Turned ON (RL = 1 kΩ)
Figure 6-3 Waveforms, Channel Being Turned OFF (RL = 1 kΩ)
Figure 6-4 OFF
Channel Leakage Current – Any Channel OFF
Figure 6-5 On Channel Leakage Current –
Any Channel On
Figure 6-6 OFF
Channel Leakage Current – All Channels OFF
Figure 6-7 Propagation Delay – Address Input to Signal Output
Figure 6-8 Propagation Delay – Inhibit Input to Signal Output
Figure 6-9 Input
Voltage Test Circuits (Noise Immunity)
Figure 6-10 Quiescent Device Current
Figure 6-11 Channel ON Resistance Measurement Circuit
Figure 6-12 Input
Current
Figure 6-13 Feed-Through (All Types)
Figure 6-14 Crosstalk Between Any Two Channels (All Types)
Figure 6-15 Crosstalk
Between Duals or Triplets (CD4052B,
CD4053B)
Special
Considerations: In applications where separate power sources are used to
drive VDD and the signal inputs, the VDD current
capability should exceed VDD/RL (RL = effective
external load). This provision avoids permanent current flow or clamp action on
the VDD supply when power is applied or removed from the CD4051B,
CD4052B or CD4053B.
Figure 6-16 Typical
Time-Division Application of the CD4052B
Figure 6-17 24-to-1
MUX Addressing