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ZHCSOB3D November 1998 – June 2021 CD54HC126 , CD74HC126

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

Add a decoupling capacitor from V_CC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the V_CC and GND pins. An example layout is shown in the GUID-7D6EDF67-B15B-4C5D-AD10-488965166051.html#GUID-7D6EDF67-B15B-4C5D-AD10-488965166051.
Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC126 to the receiving device.
Ensure the resistive load at the output is larger than (V_CC / I_O(max)) Ω. This will ensure that the maximum output current from the GUID-DCE2CCE3-221B-4462-9B51-B7037ADC4129.html#GUID-DCE2CCE3-221B-4462-9B51-B7037ADC4129 is not violated. Most CMOS inputs have a resistive load measured in megaohms; much larger than the minimum calculated above.
Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation