Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-B5332447-CF2E-4526-AC17-CF78A027D97F.html#GUID-B5332447-CF2E-4526-AC17-CF78A027D97F. The worst case resistance is calculated with the maximum input voltage, given in the GUID-DCE2CCE3-221B-4462-9B51-B7037ADC4129.html#GUID-DCE2CCE3-221B-4462-9B51-B7037ADC4129, and the maximum input leakage current, given in the GUID-B5332447-CF2E-4526-AC17-CF78A027D97F.html#GUID-B5332447-CF2E-4526-AC17-CF78A027D97F, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-66E8D3CB-F29A-4741-A425-3915FE1C0E60.html#GUID-66E8D3CB-F29A-4741-A425-3915FE1C0E60 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.