Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-603877D3-0201-4D44-B7EA-5BAC6394C625.html#GUID-603877D3-0201-4D44-B7EA-5BAC6394C625. The worst case resistance is calculated with the maximum input voltage, given in the GUID-14716D7F-CC15-4FF9-8E73-2EDC7F32D0BF.html#GUID-14716D7F-CC15-4FF9-8E73-2EDC7F32D0BF, and the maximum input leakage current, given in the GUID-603877D3-0201-4D44-B7EA-5BAC6394C625.html#GUID-603877D3-0201-4D44-B7EA-5BAC6394C625, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-0F8B1753-775E-4E6C-BC50-F6B31D197853.html#GUID-0F8B1753-775E-4E6C-BC50-F6B31D197853 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.