The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (Q_H and Q_H) available from the last stage. When the parallel load (SH/LD) input is LOW, parallel data from the A to H inputs are loaded into the register asynchronously. When the SH/LD is HIGH, data enters the register serially at the SER input and shifts one place to the right (A→B→C, etc.) with each positive-going clock transition. This feature allows parallel-to-serial converter expansion by connecting the Q_H output to the SER input of the succeeding device.

For predictable operation the LOW-to-HIGH transition of CLK INH should only take place while CLK is HIGH. Also, CLK and CLK INH should be LOW before the LOW-to-HIGH transition of SH/LD to prevent shifting the data when SH/LD goes HIGH.