米6体育平台手机版

ZHCSQV5B November 1998 – July 2022 CD54HC245 , CD54HCT245 , CD74HC245 , CD74HCT245

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机械数据 (封装 | 引脚)

J|20

散热焊盘机械数据 (封装 | 引脚)

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5.4 Electrical Characteristics

PARAMETER		TEST CONDITIONS⁽¹⁾	V_CC(V)	25°C			-40°C to 85°C		-55°C to 125°C		UNIT
PARAMETER		TEST CONDITIONS⁽¹⁾	V_CC(V)	MIN	TYP	MAX	MIN	MAX	MIN	MAX	UNIT
HC TYPES
V_IH	High-level input voltage		2	1.5			1.5		1.5		V
			4.5	3.15			3.15		3.15		V
			6	4.2			4.2		4.2		V
V_IL	Low-level input voltage		2			0.5		0.5		0.5	V
			4.5			1.35		1.35		1.35	V
			6			1.8		1.8		1.8	V
V_OH	High-level output voltage CMOS loads	I_OH = – 20 μA	2	1.9			1.9		1.9		V
		I_OH = – 20 μA	4.5	4.4			4.4		4.4		V
		I_OH = – 20 μA	6	5.9			5.9		5.9		V
	High-level output voltage TTL loads	I_OH = – 4 mA	4.5	3.98			3.84		3.7		V
	High-level output voltage TTL loads	I_OH = – 5.2 mA	6	5.48			5.48		5.2		V
V_OL	Low-level output voltage CMOS loads	I_OL = 20 μA	2			0.1		0.1		0.1	V
		I_OL = 20 μA	4.5			0.1		0.1		0.1	V
		I_OL = 20 μA	6			0.1		0.1		0.1	V
	Low-level output voltage TTL	I_OL = 4 mA	4.5			0.26		0.33		0.4	V
	Low-level output voltage TTL	I_OL = 5.2 mA	6			0.26		0.33		0.4	V
I_I	Input leakage current	V_I = V_CC or GND	6			±0.1		±1		±1	µA
I_CC	Quiescent device current	V_I = V_CC or GND	6			8		80		160	µA
I_OZ	Three-state leakage current	V_O = V_CC or GND	6			±0.5		±5		±10	µA
HCT TYPES
V_IH	High-level input voltage		4.5 to 5.5	2			2		2		V
V_IL	Low-level input voltage		4.5 to 5.5			0.8		0.8		0.8	V
V_OH	High-level output voltage CMOS loads	I_OH = – 20 μA	4.5	4.4			4.4		4.4		V
V_OH	High-level output voltage TTL	I_OH = – 4 mA	4.5	3.98			3.84		3.7		V
V_OL	Low-level output voltage CMOS	I_OL = 20 μA	4.5			0.1		0.1		0.1	V
V_OL	Low-level output voltage TTL	I_OH = 4 mA	4.5			0.26		0.33		0.4	V
I_I	Input leakage current	V_I = V_CC and GND	5.5			±0.1		±1		±1	µA
I_CC	Quiescent device current	V_I = V_CC and GND	5.5			8		80		160	µA
I_OZ	Three-state leakage current	V_O = V_CC or GND	6			±0.5		±5		±10	µA
∆I_CC⁽¹⁾	Additional quiescent device current per input pin	An or Bn input held at V_CC – 2.1 V	4.5 to 5.5		100	144		180		196	µA
		OE input held at V_CC – 2.1 V	4.5 to 5.5		100	540		675		735	µA
		DIR input held at V_CC – 2.1 V	4.5 to 5.5		100	324		405		441	µA

(1) For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA