ZHCSQ39F August   1997  – February 2022 CD54HC85 , CD54HCT85 , CD74HC85 , CD74HCT85

PRODUCTION DATA  

  1. 特性
  2. 说明
  3. Revision History
  4. Pin Configuration and Functions
  5. Specifications
    1. 5.1 Absolute Maximum Ratings (1)
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Electrical Characteristics
    5. 5.5 Switching Specifications
  6. Parameter Measurement Information
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  8. Power Supply Recommendations
  9. Layout
    1. 9.1 Layout Guidelines
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • J|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

Switching Specifications

Input tr, tf = 6 ns
PARAMETER VCC (V) 25℃ –40℃ to 85℃ –55℃ to 125℃ UNIT
MIN TYP MAX MIN MAX MIN MAX
HC TYPES
tPLH, tPHL

Propagation delay,

An, Bn to (A > B) OUT,

(A < B) OUT

2 195 245 295 ns
4.5 16(3) 39 47 59
6 33 42 50
tPLH, tPHL An, Bn to (A = B) OUT 2 175 240 265 ns
4.5 14(3) 35 44 53
6 30 37 45
tPLH, tPHL (A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT
2 140 175 210 ns
4.5 11(3) 28 35 42
6 24 30 36
tPLH, tPHL (A > B) IN to (A = B) OUT 2 120 150 180 ns
4.5 9(3) 24 30 36
6 20 26 31
CPD Power dissipation capacitance(1)(2) 5 24 pF
tTLH, tTHL Output transition times (Figure 6-1) 2 75 95 110 ns
4.5 15 19 22
6 13 16 19
CIN Input capacitance 10 10 10 pF
HCT TYPES
tPLH, tPHL

Propagation delay,

An, Bn to (A > B) OUT, (A < B) OUT

4.5 15(3) 37 46 56 ns
tPLH, tPHL An, Bn to (A = B) OUT 4.5 17(3) 40 50 60 ns
tPLH tPHL (A > B) IN, (A < B) IN, (A = B) IN
to (A > B) OUT, (A < B) OUT
4.5 12(3) 30 38 45 ns
tPLH, tPHL (A > B) IN to (A = B) OUT 4.5 13(3) 31 39 47 ns
tTLH, tTHL Output transition times (Figure 6-1) 4.5 15 19 22 ns
CPD Power dissipation capacitance(1)(2) 5 26 pF
CIN Input capacitance 10 10 10 pF
CPD is used to determine the dynamic power consumption, per gate/package.
PD = VCC2 fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
CL = 15 pF and VCC = 5 V.