ZHCSWC9A April   2003  – May 2024 CD74ACT175

PRODUCTION DATA  

  1.   1
  2. 特性
  3. 应用
  4. 说明
  5. Pin Configurations and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Operating Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Device Functional Modes
  9. Application and Implementation
    1. 8.1 Power Supply Recommendations
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
  10. Device and Documentation Support
    1. 9.1 Documentation Support (Analog)
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • N|16
  • D|16
散热焊盘机械数据 (封装 | 引脚)
订购信息

Parameter Measurement Information

CD74ACT175 Load Circuit and Voltage
                    Waveforms Figure 6-1 Load Circuit and Voltage Waveforms
CL includes probe and test-fixture capacitance.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary.
For clock inputs, fmax is measured with the input duty cycle at 50%.
The outputs are measured one at a time with one input transition per measurement.
tPLH and tPHL are the same as tpd.
tPZL and tPZH are the same as ten.
tPLZ and tPHZ are the same as tdis.
All parameters and waveforms are not applicable to all devices.
TEST S1
tPLH/tPHL Open
tPLZ/tPZL 2 × VCC
tPHZ/tPZH GND