ZHCSWD1C December 2023 – May 2024 CD54AC240 , CD54AC244 , CD54ACT240 , CD54ACT241 , CD54ACT244 , CD74AC240 , CD74AC244 , CD74ACT240 , CD74ACT241 , CD74ACT244
PRODUCTION DATA
请参考 PDF 数据表获取器件具体的封装图。
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more convenient. It is generally okay to float outputs unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This does not disable the input section of the IOs so they cannot float when disabled.