Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-57FB1C17-23BD-429C-BB02-7DBDF8F1BE6A.html#GUID-57FB1C17-23BD-429C-BB02-7DBDF8F1BE6A. The worst case resistance is calculated with the maximum input voltage, given in the GUID-7A04E054-1216-4CA3-901D-1837146D67B0.html#GUID-7A04E054-1216-4CA3-901D-1837146D67B0, and the maximum input leakage current, given in the GUID-57FB1C17-23BD-429C-BB02-7DBDF8F1BE6A.html#GUID-57FB1C17-23BD-429C-BB02-7DBDF8F1BE6A, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-D303D718-A42D-48B5-9FD2-47278EBFFCF8.html#GUID-D303D718-A42D-48B5-9FD2-47278EBFFCF8 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.