Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-F374DB1A-427A-448A-8A2A-C366935A4372.html#GUID-F374DB1A-427A-448A-8A2A-C366935A4372. The worst case resistance is calculated with the maximum input voltage, given in the GUID-4425E636-39D5-4640-89C4-983432F7C8BC.html#GUID-4425E636-39D5-4640-89C4-983432F7C8BC, and the maximum input leakage current, given in the GUID-F374DB1A-427A-448A-8A2A-C366935A4372.html#GUID-F374DB1A-427A-448A-8A2A-C366935A4372, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-5889E3DE-5DD3-46B1-94CB-11E6E33DA42F.html#GUID-5889E3DE-5DD3-46B1-94CB-11E6E33DA42F to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.