Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-26F277F0-6E90-431A-B4F9-31CC4B1AA65F.html#GUID-26F277F0-6E90-431A-B4F9-31CC4B1AA65F. The worst case resistance is calculated with the maximum input voltage, given in the GUID-B1755536-FEFA-483A-8445-2D8287DD9CF6.html#GUID-B1755536-FEFA-483A-8445-2D8287DD9CF6, and the maximum input leakage current, given in the GUID-26F277F0-6E90-431A-B4F9-31CC4B1AA65F.html#GUID-26F277F0-6E90-431A-B4F9-31CC4B1AA65F, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-23EDA0A5-A76A-40B3-A0F9-D6E5C7D96ACD.html#GUID-23EDA0A5-A76A-40B3-A0F9-D6E5C7D96ACD to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.