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ZHCSPY5A January 2004 – February 2022 CD74HC595

PRODUCTION DATA

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

DB|16
NS|16
DW|16
N|16
D|16

散热焊盘机械数据 (封装 | 引脚)

DW|16
- QFND313D

订购信息

5.5 Timing Requirements

PARAMETER			V_CC (V)	25°C		-40°C to 85°C		-55°C to 125°C		UNIT
PARAMETER			V_CC (V)	MIN	MAX	MIN	MAX	MIN	MAX	UNIT
HC TYPES
f_clock	Clock frequency		2		6		5		4.2	MHz
			4.5		31		25		21
			6		36		29		25
t_W	Pulse duration	SRCLK or RCLK high or low	2	80		100		120		ns
			4.5	16		20		24
			6	14		17		20
		SRCLR low	2	80		100		120
			4.5	16		20		24
			6	14		17		20
t_SU	Setup time	SER before SRCLK↑	2	100		125		150		ns
			4.5	20		25		30
			6	17		21		25
		SRCLK↑ before RCLK↑⁽¹⁾	2	75		94		113
			4.5	15		19		23
			6	13		16		19
		SRCLR low before RCLK↑	2	50		65		75
			4.5	10		13		15
			6	9		11		13
		SRCLR high (inactive) before SRCLK↑	2	50		60		75
			4.5	10		12		15
			6	9		11		13
t_h	Hold time, SER after SRCLK↑		2	0		0		0		ns
			4.5	0		0		0
			6	0		0		0

(1) This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case the shift register is one clock pulse ahead of the storage register.