Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-AAE73095-0E9A-4B1E-B8ED-BDC1EE66A7FB.html#GUID-AAE73095-0E9A-4B1E-B8ED-BDC1EE66A7FB. The worst case resistance is calculated with the maximum input voltage, given in the GUID-C929ED3C-E55B-4AB4-BCB3-1222A71B8D2E.html#GUID-C929ED3C-E55B-4AB4-BCB3-1222A71B8D2E, and the maximum input leakage current, given in the GUID-AAE73095-0E9A-4B1E-B8ED-BDC1EE66A7FB.html#GUID-AAE73095-0E9A-4B1E-B8ED-BDC1EE66A7FB, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-E706253B-DFF1-4D37-B126-68B3596B8971.html#GUID-E706253B-DFF1-4D37-B126-68B3596B8971 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.