Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-956EC158-5E84-4546-887E-5272719B0C54.html#GUID-956EC158-5E84-4546-887E-5272719B0C54. The worst case resistance is calculated with the maximum input voltage, given in the GUID-378DC7B7-9B8B-4B07-8207-6527EA907691.html#GUID-378DC7B7-9B8B-4B07-8207-6527EA907691, and the maximum input leakage current, given in the GUID-956EC158-5E84-4546-887E-5272719B0C54.html#GUID-956EC158-5E84-4546-887E-5272719B0C54, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-01D50F7D-A466-4535-9A1C-526BA2E53E4D.html#GUID-01D50F7D-A466-4535-9A1C-526BA2E53E4D to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.