Standard CMOS inputs are high impedance and are typically modeled as a resistor from the input to ground in parallel with the input capacitance given in the GUID-4AE2704F-BC23-4E82-B638-7DA89CA38518.html#GUID-4AE2704F-BC23-4E82-B638-7DA89CA38518. The worst case resistance is calculated with the maximum input voltage, given in the GUID-86F192CC-331B-43C7-B7BD-86BD96FE6F3A.html#GUID-86F192CC-331B-43C7-B7BD-86BD96FE6F3A, and the maximum input leakage current, given in the GUID-4AE2704F-BC23-4E82-B638-7DA89CA38518.html#GUID-4AE2704F-BC23-4E82-B638-7DA89CA38518, using ohm's law (R = V ÷ I).

Signals applied to the inputs need to have fast edge rates, as defined by the input transition time in the GUID-17AF669B-358A-4991-AE39-9988A88FD189.html#GUID-17AF669B-358A-4991-AE39-9988A88FD189 to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.