The CD74HC390 and ’HCT390 dual 4-bit decade ripple counters are high-speed silicon-gate CMOS devices and are pin compatible with low-power Schottky TTL (LSTTL). These devices are divided into four separately clocked sections. The counters have two divide-by-2 sections and two divide-by-5 sections. These sections are normally used in a BCD decade or bi-quinary configuration, since they share a common controller reset (nCLR). If the two controller reset inputs (1CLR and 2CLR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package. The separate clock inputs (nCLK_A and nCLK_B) of each section allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50, or 100. Each section is triggered by the High-to-Low transition of the input pulses (nCLK_A and nCLK_B).

For BCD decade operation, the nQ_A output is connected to the nCLK_B input of the divide-by-5 section. For bi-quinary decade operation, the nQ_D output is connected to the nCLK_A input and nQ_A becomes the decade output.

The controller reset inputs (1CLR and 2CLR) are active-High asynchronous inputs to each decade counter which operates on the portion of the counter identified by the “1” and “2” prefixes in the pin configuration. A High level on the nCLR input overrides the clock and sets the four outputs Low.