米6体育平台手机版

ZHCSKG8A November 2019 – February 2020 CDCDB2000

PRODUCTION DATA.

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机械数据 (封装 | 引脚)

NPP|80
- MPBGAP1

散热焊盘机械数据 (封装 | 引脚)

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Table 5. Electrical Characteristics

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
CURRENT CONSUMPTION
I_{DD_A}	Core supply current	Active mode. CKPWRGD_PD# = 1			12		mA
I_{DD_A}	Core supply current	Power down mode. CKPWRGD_PD# = 0			8		mA
I_DD	IO supply current per output	All-outputs disabled			20		mA
		All-outputs active, 100MHz			200
		Power down mode. CKPWRGD_PD# = 0			8
CLOCK INPUT
f_IN	Input frequency			50	100	250	MHz
V_IN	Input voltage swing	Differential voltage between CLKIN_P and CLKIN_N⁽¹⁾		200		2300	mV_Diff-peak
dV/dt	Input voltage edge rate	20% - 80% of input swing		0.7			V/ns
DV_CROSS	Total variation of V_CROSS	Total variation across V_CROSS			140		mV
DC_IN	Input duty cycle			40		60	%
C_IN	Input capacitance⁽²⁾	Differential capacitance between CLKIN_P and CLKIN_N pins			2.2		pF
CLOCK OUTPUT
f_OUT	Output frequency			50	100	250	MHz
C_OUT	Output capacitance⁽¹⁾	Differential capacitance between CKx_P and CKx_N pins			2.2		pF
V_OH	Output high voltage	Single-ended⁽²⁾⁽³⁾		225		270	mV
V_OL	Output low voltage	Single-ended⁽²⁾⁽³⁾		10		150
V_CROSS	Crossing point voltage	Input V_CROSS varied by 140 mV. ⁽³⁾⁽⁴⁾		130		200
DV_CROSS	Total variation of V_CROSS	Input V_CROSS varied by 140 mV. Variation of V_CROSS⁽³⁾⁽⁴⁾				35
V_ovs	Overshoot voltage	⁽³⁾				V_OH+75
V_uds	Undershoot voltage	⁽³⁾				V_OL–75
Z_DIFF	Differential impedance	Measured at V_OL/V_OH		81	85	89	ohm
Z_{DIFF_CROSS}	Differential impedance	Measured at V_CROSS		68	85	102	ohm
t_EDGE	Edge rate	Measured at V_CROSS		2		20	V/ns
Dt_EDGE	Edge rate matching	Measured at V_CROSS				20	%
t_STABLE	Power good assertion to stable clock output	CKPWRGD_PD# pin transistions from 0 to 1, f_IN = 100 MHz	Measured when PWRGD reaches 0.2V			1.8	ms
t_{DRIVE_PD#}	Power good assertion to outputs driven high	CKPWRGD_PD# pin transistions from 0 to 1, f_IN = 100 MHz	Measured when PWRGD reaches 0.2V			300	µs
t_OE	Output enable assertion to stable clock output	OEx# pin transistions from 1 to 0				10	CLKIN Periods
t_OD	Output enable de-assertion to no clock output	OEx# pin transistions from 0 to 1				10
t_PD	Power down assertion to no clock output	CKPWRGD_PD# pin transistions from 1 to 0				3
t_DCD	Duty cycle distortion	Differential; f_IN = 100MHz, f_{in_DC} = 50%		–1.0		1.0	%
t_DLY	Propagation delay	⁽⁵⁾		0.5		3	ns
t_SKEW	Skew between outputs	⁽⁶⁾				50	ps
J_{CKx_PCIE}	Additive jitter	DB2000QL filter				0.08	ps, rms
	Additive jitter for PCIe5	PCIe5.0 filter				0.03	ps, rms
	Additive jitter for PCIe4	PLL BW = 2 - 5 MHz; CDR = 10 MHz	Input clock slew rate ≥ 1.8 V/ns			0.08	ps, rms
	Additive jitter for PCIe3	PLL BW = 2 - 5 MHz; CDR = 10 MHz	Input clock slew rate ≥ 0.6 V/ns			0.15	ps, rms
J_{CKx_PCIE}	Additive jitter for PCIe2	PCIe2 filter				0.2	ps, rms
J_{CKx_PCIE}	Additive jitter for PCIe1	PCIe1 filter				5	ps, rms
J_CKx	Additive jitter	f_IN = 100 MHz; slew rate ≥ 3 V/ns; 12 kHz to 20 MHz integration bandwidth.			155		fs, rms
SMBUS INTERFACE, SIDE-BAND INTERFACE, OEx#, CKPWRGD_PD#, SBEN
V_IH	High-level input voltage			2.0			V
V_IL	Low-level input voltage					0.8	V
I_IL	Input leakage current	With internal pull up/pull-down	GND < V_IN < V_DD	–30		30	uA
I_IL	Input leakage current	Without internal pull up/pull-down	GND < V_IN < V_DD	–5		5	uA
C_IN	Input capacitance				4.5		pF
C_OUT	Output capacitance				4.5		pF
3-LEVEL DIGITAL INTERFACE (SA_0, SA_1)
V_IHT	High-level input voltage			2.4			V
V_IMT	Mid level input voltage			1.3	V_DD/2	1.8
V_ILT	Low-level input voltage					0.9
I_INT	Input high current	VIN = V_DD, VIN = GND		-10		10	uA
I_Leak	Input leakage current	With internal pull up/pull-down	GND < V_IN < V_DD	–30		30	uA

(1) Voltage swing includes overshoot.

(2) Not tested in production. Ensured by design and characterization.

(3) Measured into DC test load.

(4) V_CROSS is single-ended voltage when CKx_P = CKx_N with respect to system ground. Only valid on rising edge of CKx, when CKx_P is rising.

(5) Measured from rising edge of CLK_IN to any CKx output.

(6) Measured from rising edge of any CKx output to any other CKx output.