ZHCSKG8A November   2019  – February 2020 CDCDB2000

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      CDCDB2000 系统图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. Table 1. Absolute Maximum Ratings
    2. Table 2. ESD Ratings
    3. Table 3. Recommended Operating Conditions
    4. Table 4. Thermal Information
    5. Table 5. Electrical Characteristics
    6. Table 6. Timing Requirements
    7. 6.1      Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Output Enable Control
      2. 7.3.2 SMBus
        1. 7.3.2.1 SMBus Address Assignment
      3. 7.3.3 Side-Band Interface
    4. 7.4 Device Functional Modes
      1. 7.4.1 CKPWRGD_PD# Function
      2. 7.4.2 OE[12:5]# and SMBus Output Enables
    5. 7.5 Programming
      1. 7.5.1 SMBus
      2. 7.5.2 SBI
    6. 7.6 Register Maps
      1. 7.6.1 CDCDB2000 Registers
        1. 7.6.1.1  OECR1 Register (Address = 0h) [reset = 78h]
          1. Table 11. OECR1 Register Field Descriptions
        2. 7.6.1.2  OECR2 Register (Address = 1h) [reset = FFh]
          1. Table 12. OECR2 Register Field Descriptions
        3. 7.6.1.3  OECR3 Register (Address = 2h) [reset = FFh]
          1. Table 13. OECR3 Register Field Descriptions
        4. 7.6.1.4  OERDBK Register (Address = 3h) [reset = 0h]
          1. Table 14. OERDBK Register Field Descriptions
        5. 7.6.1.5  SBRDBK Register (Address = 4h) [reset = 1h]
          1. Table 15. SBRDBK Register Field Descriptions
        6. 7.6.1.6  VDRREVID Register (Address = 5h) [reset = X]
          1. Table 16. VDRREVID Register Field Descriptions
        7. 7.6.1.7  DEVID Register (Address = 6h) [reset = X]
          1. Table 17. DEVID Register Field Descriptions
        8. 7.6.1.8  BTRDCNT Register (Address = 7h) [reset = 8h]
          1. Table 18. BTRDCNT Register Field Descriptions
        9. 7.6.1.9  SBIMSK1 Register (Address = 8h) [reset = 0h]
          1. Table 19. SBIMSK1 Register Field Descriptions
        10. 7.6.1.10 SBIMSK2 Register (Address = 9h) [reset = 0h]
          1. Table 20. SBIMSK2 Register Field Descriptions
        11. 7.6.1.11 SBIMSK3 Register (Address = Ah) [reset = 0h]
          1. Table 21. SBIMSK3 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Enable Control Method
        2. 8.2.2.2 SMBus Address
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 TICS Pro
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 Glossary
  12. 12机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

8.2.1 Design Requirements

Consider a typical server motherboard application which needs to distribute a 100-MHz PCIe reference clock from the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:

  • Clock Input:
    • 100-MHz LP-HCSL
  • Clock Output:
    • 2x 100-MHz to processors, LP-HCSL
    • 2x 100-MHz to riser/retimer, LP-HCSL
    • 2x 100-MHz to DDR memory controller, LP-HCSL

The section below describes the design procedure to configure the CDCDB2000 to output the frequencies for the above scenario.
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