ZHCSKG8B November   2019  – October 2024 CDCDB2000

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Output Enable Control
      2. 6.3.2 SMBus
        1. 6.3.2.1 SMBus Address Assignment
      3. 6.3.3 Side-Band Interface
    4. 6.4 Device Functional Modes
      1. 6.4.1 CKPWRGD_PD# Function
      2. 6.4.2 OE[12:5]# and SMBus Output Enables
    5. 6.5 Programming
      1. 6.5.1 SMBus
      2. 6.5.2 SBI
  8. 7 Register Maps
    1. 7.1 CDCDB2000 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Output Enable Control Method
        2. 8.2.2.2 SMBus Address
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 TICS Pro
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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6.3.2.1 SMBus Address Assignment

The SMBus address is assigned by configuration of two pins (SADR1 and SADR0) that each support three levels. This configuration allows the CDCDB2000 to assume 9 different SMBus addresses.

The SMBus address pins are sampled PWRGD is set to 1. See Table 6-1 for address pin configuration. The address cannot be changed until the PWRGD state is cleared by powering down the device.

Table 6-1 SMBus Address Assignment
SADR1 SADR0 SMBUS ADDRESS
L L 0xD8
L M 0xDA
L H 0xDE
M L 0xC2
M M 0xC4
M H 0xC6
H L 0xCA
H M 0xCC
H H 0xCE
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