The CDCDB2000 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict performance requirements for PCIe Gen 1-5, QPI and UPI reference clocks. The CDCDB2000 allows buffering and replication of a single clock source to up to 20 individual outputs in the LP-HCSL format. The outputs of the CDCDB2000 can be configured before they are enabled using the Side-Band control interface. The CDCDB2000 also includes status and control registers accessible by an SMBus version 2.0 compliant interface. The device integrates a large amount of external passive components to reduce overall system cost.