Consider a typical server motherboard application which needs to distribute a 100-MHz PCIe reference clock from the PCH of a processor chipset to multiple endpoints. An example of clock input and output requirements is:

• Clock Input:
  • 100-MHz LP-HCSL
• Clock Output:
  • 2x 100-MHz to processors, LP-HCSL
  • 2x 100-MHz to riser/retimer, LP-HCSL
  • 2x 100-MHz to DDR memory controller, LP-HCSL

The section below describes the design procedure to configure the CDCDB2000 to output the frequencies for the above scenario.