米6体育平台手机版

ZHCSKG8B November 2019 – October 2024 CDCDB2000

PRODUCTION DATA

5.6 Timing Requirements

VDD, VDD_A = 3.3 V ± 5 %, -40 °C < TA < 85 °C. Typical values are at VDD = VDD_A = 3.3 V, 25 °C (unless otherwise noted)

			MIN	MAX	UNIT
SMBUS-COMPATIBLE INTERFACE TIMING
f_SMB	SMBus operating frequency		10	100	kHz
t_BUF	Bus free time between STOP and START		4.7		µs
t_{HD_STA}	START condition hold time		4
t_{SU_STA}	START condition setup time		4.7
t_{SU_STO}	STOP condition setup time		4
t_{HD_DAT}	SMBDAT hold time		300		ns
t_{SU_DAT}	SMBDAT setup time		250		ns
t_TIMEOUT	Detect SMBCLK low timeout		25	35	ms
t_LOW	SMBCLK low period		4.7		µs
t_HIGH	SMBCLK high period		4	50	µs
t_{LOW_SL}	Cumulative clock low extend time			25	ms
t_F	SMBCLK/SMBDAT fall time⁽¹⁾			300	ns
t_R	SMBCLK/SMBDAT rise time⁽²⁾			1000	ns
SIDE-BAND INTERFACE TIMING
t_PERIOD	Clock period		40		ns
t_SETUP	Setup time to clock		25
t_DSU	Data set up time		10
t_DHOLD	Data hold time		5
t_DELAY	Delay time		25
t_PDLY	Propagation delay		4	10	CLK periods
t_SLEW	Clock slew rate	20% - 80%	0.2	3	V/ns

(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

(2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15)