4 Pin Configuration and Functions

CDCDB2000 CDCDB2000 NPP Package80-Pin TLGATop View

Figure 4-1 CDCDB2000 NPP Package80-Pin TLGATop View

Table 4-1 Pin Functions

PIN		I/O TYPE⁽²⁾	DESCRIPTION
NAME⁽¹⁾	NO.	I/O TYPE⁽²⁾	DESCRIPTION
INPUT CLOCK
CLKIN_P	G1	I	LP-HCSL differential clock input. Typically connected directly to the differential output of clock source.
CLKIN_N	H1	I
OUTPUT CLOCKS
CK0_P	J1	O	LP-HCSL differential clock output of channel 0. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK0_N	K1	O
CK1_P	L1	O	LP-HCSL differential clock output of channel 1. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK1_N	M1	O
CK2_P	M2	O	LP-HCSL differential clock output of channel 2. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK2_N	M3	O
CK3_P	M4	O	LP-HCSL differential clock output of channel 3. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK3_N	M5	O
CK4_P	M7	O	LP-HCSL differential clock output of channel 4. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK4_N	M8	O
CK5_P	M9	O	LP-HCSL differential clock output of channel 5. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin L8 (OE5# / DATA) is recommended to be either in DATA mode or pulled high.
CK5_N	M10	O
CK6_P	M11	O	LP-HCSL differential clock output of channel 6. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin L10 (OE6# / CLK) is recommended to be either in CLK mode or pulled high.
CK6_N	M12	O
CK7_P	L12	O	LP-HCSL differential clock output of channel 7. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin K11 (OE7#) is recommended to be pulled high to disable channel 7 output.
CK7_N	K12	O
CK8_P	J12	O	LP-HCSL differential clock output of channel 8. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin H11 (OE8#) is recommended to be pulled high to disable channel 8 output.
CK8_N	H12	O
CK9_P	G12	O	LP-HCSL differential clock output of channel 9. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin E12 (OE9#) is recommended to be pulled high to disable channel 9 output.
CK9_N	F12	O
CK10_P	D12	O	LP-HCSL differential clock output of channel 10. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin E11 (OE10# / SHFT_LD#) is recommended to be either in SHFT_LD# mode or pulled high.
CK10_N	C12	O
CK11_P	B12	O	LP-HCSL differential clock output of channel 11. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin C11 (OE11#) is recommended to be pulled high to disable channel 11 output.
CK11_N	A12	O
CK12_P	A11	O	LP-HCSL differential clock output of channel 12. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect, and pin B10 (OE12#) is recommended to be pulled high to disable channel 12 output.
CK12_N	A10	O
CK13_P	A9	O	LP-HCSL differential clock output of channel 13. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK13_N	A8	O
CK14_P	A7	O	LP-HCSL differential clock output of channel 14. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK14_N	A6	O
CK15_P	A5	O	LP-HCSL differential clock output of channel 15. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK15_N	A4	O
CK16_P	A3	O	LP-HCSL differential clock output of channel 16. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK16_N	A2	O
CK17_P	A1	O	LP-HCSL differential clock output of channel 17. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK17_N	B1	O
CK18_P	C1	O	LP-HCSL differential clock output of channel 18. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK18_N	D1	O
CK19_P	E1	O	LP-HCSL differential clock output of channel 19. Typically connected directly to PCIe differential clock input. If unused, the pins can be left no connect.
CK19_N	F1	O
MANAGEMENT AND CONTROL
CKPWRGD_PD#	M6	I, PD	Clock Power Good and Power Down multi-function input pin with internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. On first high transition, PWRGD samples the latched SADR[1:0] inputs and starts up device. After PWRGD has been asserted high for the first time, the pin becomes a PD# pin and it controls power-down mode: LOW: Power-down mode, all output channels tri-stated. HIGH: Normal operation mode.
OE5# DATA	L8	I, PD	Output enable for channel 5 and Side-Band Interface data multi-function pin with internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both modes are unused, the pin can be left no connect. When pin E2 = LOW, OE5# mode. Output enable for channel 5, active low. LOW: enable output channel 5. HIGH: disable output channel 5. When pin E2 = HIGH, DATA mode. Side-Band Interface data pin.
OE6# CLK	L10	I, PD	Output enable for channel 6 and Side-Band Interface clock multi-function pin with internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both modes are unused, the pin can be left no connect. When pin E2 = LOW, OE6# mode. Output Enable for channel 6, active low. LOW: enable output channel 6. HIGH: disable output channel 6. When pin E2 = HIGH, CLK mode. Side-Band interface clock pin.
OE7#	K11	I, PD	Output Enable for channel 7 with internal 120-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 7. HIGH: disable output channel 7.
OE8#	H11	I, PD	Output Enable for channel 8, with internal 120-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 8. HIGH: disable output channel 8.
OE9#	E12	I, PD	Output Enable for channel 9, with internal 120-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 9. HIGH: disable output channel 9.
OE10# SHFT_LD#	E11	I, PD	Output enable for channel 10 and Side-Band Interface load shift registers multi-function pin with internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If both modes are unused, the pin can be left no connect. When pin E2 = LOW, OE10# mode. Output Enable for channel 10, active low. LOW: enable output channel 10. HIGH: disable output channel 10. When pin E2 = HIGH, SHFT_LD# mode. Side-Band Interface load shift registers pin. LOW: disable Side-Band Interface shift register. HIGH: enable Side-Band Interface shift register. A falling edge transfers the Side-Band shift register contents to the output register.
OE11#	C11	I, PD	Output Enable for channel 11 with internal 120-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 11. HIGH: disable output channel 11.
OE12#	B10	I, PD	Output Enable for channel 12 with internal 120-kΩ pulldown, active low. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. LOW: enable output channel 12. HIGH: disable output channel 12.
SBEN	E2	I, S, PD	Side-Band Interface enable input with internal 120-kΩ pulldown. Typically connected to GPIO of microcontroller. If unused, the pin can be left no connect. This pin disables the Output Enable (OE#) pins when asserted. LOW: OE# pins and SMBus enable bits control outputs, Side-Band interface disabled. HIGH: Side-Band Interface controls outputs, OE# pins and SMBus enable bits are disabled.
SMBUS AND SMBUS ADDRESS
SADR0	B4	I, S, PU / PD	SMBus address strap bit[0]. This is a 3-level input that is decoded in conjunction with pin B8 to set SMBus address. It has internal 120-kΩ pullup / pulldown network biasing to VDD/2 when no connect. For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance. For a low-level input configuration input, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance. For a mid-level input configuration, the pin should be left floating and not connected to VDD or ground.
SADR1	B8	I, S, PU / PD	SMBus address strap bit[1]. This is a 3-level input that is decoded in conjunction with pin B4 to set SMBus address. It has internal 120-kΩ pullup / pulldown network biasing to VDD/2 when no connect. For a high-level input configuration, the pin should be pulled up to 3.3-V VDD through an external pullup resistor from 1k to 5k with 5% tolerance. For a low-level input configuration, the pin should be pulled down to ground through an external pulldown resistor from 1k to 5k with 5% tolerance. For a mid-level input configuration, the pin should be left floating and not connected to VDD or ground.
SMBCLK	L5	I	Clock pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k.
SMBDAT	L4	I / O	Data pin of SMBus interface. Typically pulled up to 3.3-V VDD using external pullup resistor. The recommended pullup resistor value is > 8.5k.
SUPPLY VOLTAGE AND GROUND
GND	DAP	G	Ground. Connect ground pad to system ground.
VDD	B2, B6, B11, L2, L11	P	Power supply input for LP-HCSL clock output channels. Connect to 3.3-V power supply rail with decoupling capacitor to GND. Place a 0.1-µF capacitor close to each supply pin between power supply and ground.
VDD_A	H2	P	Power supply input for differential input clock. Connect to 3.3-V power supply rail with decoupling capacitor to GND. Place a 0.1-µF capacitor close to pin.
NO CONNECT
NC	B3, B5, B7, B9, C2, D2, D11, F2, F11, G2, G11, J2, J11, K2, L3, L6, L7, L9,	—	Do not connect to GND or VDD.

(1) The “#” symbol at the end of a pin name indicates that the active state occurs when the signal is at a low voltage level. When “#” is not present, the signal is active high.

(2) The definitions below define the I/O type for each pin.

I = Input
O = Output
I / O = Input / Output
PU / PD = Internal 120-kΩ Pullup / Pulldown network biasing to VDD/2
PD = Internal 120-kΩ Pulldown
S = Hardware Configuration Pin
P = Power Supply
G = Ground