米6体育平台手机版

ZHCSOD8A November 2021 – May 2022 CDCDB400

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

RHB|32
- MPQF130D

散热焊盘机械数据 (封装 | 引脚)

RHB|32
- QFND029X

订购信息

8.4.2 OE[3:0]# and SMBus Output Enables

Each output channel, 0 to 3, can be individually enabled or disabled by a SMBus control register bit, called SMB enable bits. Additionally, each output channel has a dedicated, corresponding, OE[3:0]# hardware pin. The OE[3:0]# pins are asynchronously asserted-low signals that may enable or disable the output.

Refer to Table 8-2 for enabling and disabling outputs through the hardware and software. Note that both the SMB enable bit must be a 1 and the OEx# pin must be an input low voltage 0 for the output channel to be active.

Table 8-2 OE[3:0]# Functionality

Control Inputs	Power State Variables (Internal)		CLKIN	OE[3:0]# HARDWARE PINS AND SMBus CONTROL REGISTER BITS			CK[3:0]_P/CK[3:0]_N
CKPWRGD_PD#	PWRGD	PD#	CLKIN	OE[3:0]#	OUT_EN_CLK[3:0]	DRIVE_OP_STATE_CTRL	CK[3:0]_P/CK[3:0]_N
0	0	0	X	X	X	X	LOW/LOW
1	1	1	X⁽¹⁾	X	0	0	LOW/LOW
				X	0	1	TRI-STATE
				1	X	0	LOW/LOW
				1	X	1	TRI-STATE
			Running⁽¹⁾	0	1	X	Running
0		0	X⁽²⁾	X	X	0	LOW/LOW
0		0	X⁽²⁾	X	X	1	TRI-STATE

(1) To enter the power-down state, CLKIN must remain active for at least 3 clock cycles after CKPWRGD_PD# transitions from 1 to 0.

(2) To enter the powered-up state with active clock outputs, CLKIN must be active before CKPWRGD_PD# transitions from 0 to 1.