Figure 6-1 shows both the phase noise of the source as well as the output of the DUT (CDCDB400). It can be seen from the phase noise plot that the DUT has a very low phase noise profile with total jitter of 81.5 fs, rms. If we rms subtract the clock reference noise, the additive jitter of CDCDB400 under typical conditions would be lower than 81.5 fs, rms.

Figure 6-1 CDCDB400 Clock Out (CK0:4) Phase Noise