The CDCDB400 is a low additive-jitter, low propagation delay clock buffer designed to meet the strict performance requirements for PCIe Gen 1-6, QPI, UPI, SAS, and SATA reference clocks in CC, SRNS, or SRIS architectures. The CDCDB400 allows buffering and replication of a single clock source to up to four individual outputs in the LP-HCSL format. The CDCDB400 also includes status and control registers accessible by an SMBus version 2.0 compliant interface. The device integrates a large amount of external passive components to reduce overall system cost.