米6体育平台手机版

ZHCSOD8A November 2021 – May 2022 CDCDB400

PRODUCTION DATA

6.6 Timing Requirements

VDD, VDD_R = 3.3 V ± 5 %, −40°C ≤ T_A ≤ 85°C. Typical values are at VDD = VDD_R = 3.3 V, 25°C (unless otherwise noted)

			MIN	MAX	UNIT
SMBUS COMPATIBLE INTERFACE TIMING
f_SMB	SMBus operating frequency		10	400	kHz
t_BUF	Bus free time between STOP and START		4.7		µs
t_{HD_STA}	START condition hold time	SMBCLK low after SMBDAT low	4
t_{SU_STA}	START condition setup time	SMBCLK high before SMBDAT low	4.7
t_{SU_STO}	STOP condition setup time		4
t_{HD_DAT}	SMBDAT hold time		300		ns
t_{SU_DAT}	SMBDAT setup time		250		ns
t_TIMEOUT	Detect SMBCLK low timeout	In terms of device input clock frequency	1e6		cycles
t_LOW	SMBCLK low period		4.7		µs
t_HIGH	SMBCLK high period		4	50	µs
t_F	SMBCLK/SMBDAT fall time⁽¹⁾			300	ns
t_R	SMBCLK/SMBDAT rise time⁽²⁾			1000	ns

(1) TF = (VIHMIN + 0.15) to (VILMAX - 0.15)

(2) TR = (VILMAX - 0.15) to (VIHMIN + 0.15)