Figure 6-1 shows both the phase noise of the source as well as the output of the DUT (CDCDB803). It can be seen from the phase noise plot that the DUT has a very low phase noise profile with total jitter of 71 fs, rms. If we rms subtract the clock reference noise, the additive jitter of CDCDB803 under typical conditions would be lower than 71 fs, rms.

Figure 6-1 CDCDB803 Clock Out (CK0:8) Phase Noise