The output dividers can be reset in a deterministic way. This can be achieved using the sync bit or PDN pin. The level of the pin is qualified internally using the reference frequency at the PFD input. A low level on the SYNCN pin or sync bit will mute the outputs. A high level will synchronously release all output dividers to operation, so that all outputs share a common rising edge. The first rising edge can be individually delayed in steps of the respective pre-scalar period, up to 32 cycles using ch{x}_sync_delay. This allows the user to compensate external delays like routing mismatch, cables, or inherent delays introduced by logic gates in an FPGA design. Each channel can be included or excluded from the SYNC process. Divider synchronization can be enabled individually by ch{x}_sync_en.

For a deterministic behavior over power-cycles seen from input to output the reference divider must be set to 1. It should not divide the reference clock nor should the reference doubler be used.

Figure 9-9 Output Divider Synchronization