米6体育平台手机版

ZHCSK34B July 2020 – October 2021 CDCE6214-Q1

PRODUCTION DATA

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请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)

RGE|24

散热焊盘机械数据 (封装 | 引脚)

订购信息

7.17 LVCMOS Output Characteristics

VDD_VCO, VDDO_12, VDDO_34, VDD_REF = 1.8 V ± 5%, 2.5 V ± 5%, 3.3 V ± 5% and T_A = -40°C to 105°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
f_{O_LVCMOS}	Output frequency	2 pF to GND, normal mode	0.024		200	MHz
V_{OH_LVCMOS}	Output high voltage	I_OH = 1 mA, VDDO_x is corresponding supply voltage.	0.8 × VDDO_x			V
V_{OL_LVCMOS}	Output low voltage	I_OL = 1 mA, VDDO_x is corresponding supply voltage.			0.2 × VDDO_x	V
I_OH	Output high current	Vout = 0.8 × VDDO_x, VDDO_x = 1.8 V		-6		mA
I_OH	Output high current	Vout = 0.8 × VDDO_x, VDDO_x = 2.5 V		-8.5		mA
I_OH	Output high current	Vout = 0.8 × VDDO_x, VDDO_x = 3.3 V		-11.2		mA
I_OL	Output low current	Vout = 0.2 × VDDO_x, VDDO_x = 1.8 V		6		mA
I_OL	Output low current	Vout = 0.2 × VDDO_x, VDDO_x = 2.5 V		8.5		mA
I_OL	Output low current	Vout = 0.2 × VDDO_x, VDDO_x = 3.3 V		11.2		mA
T_RISE-FALL	Output rise/fall time	20/80%, C_L= 5 pF, normal mode	300	500	700	ps
T_RISE-FALL	Output rise/fall time	20/80%, C_L= 5 pF, slow mode, measured on OUT0		1000		ps
T_SKEW	Output-to-output skew⁽¹⁾	LVCMOS-to-LVCMOS outputs, same divide value		100		ps
T_SKEW	Output-to-output skew⁽¹⁾	LVCMOS-to-Differential outputs, same divide value		400		ps
ODC	Output duty cycle	Not in PLL bypass mode	45		55	%
R_{ON_LVCMOS}	Output impedance	Normal mode	45	60	75	Ω
R_{ON_LVCMOS}	Output impedance	Slow mode	50	65	85	Ω

(1) OUT1/OUT4 and OUT2/OUT3 are matched pair-wise. OUT1/OUT4 has LVCMOS buffer while OUT2/OUT3 do not have LVCMOS buffer. OUT1/OUT4 is matched within T_OUT-SKEW. OUT2/OUT3 is matched within T_OUT-SKEW.