米6体育平台手机版

ZHCSK34B July 2020 – October 2021 CDCE6214-Q1

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RGE|24

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9.3.3 Clock Distribution

The VCO output connects to two individually configurable pre-scalar dividers sourcing the on-chip clock distribution – PSA and PSB. PSA and PSB can be configured as division value of /4, /5 or /6 independently.

The clock distribution consists of four output channels. Each output channel contains an integer divider (IOD) with glitchless switching and synchronization capabilities.

IOD can be sourced from either the PSA, the PSB, or the Reference Clock. IOD can be bypassed to provide a Reference clock at the output.

There are five output channels – OUT0, OUT1, OUT2, OUT3, and OUT4.

The OUT0 is a slew-rate controllable LVCMOS output. Either the reference clock or PFD clock can be routed to this output through the clock distribution network.

The OUT1 and OUT4 are identical output channels. The output buffers in this channel are compatible with various signaling standards – LVCMOS, LP-HCSL, and LVDS-like.

The OUT2 and OUT3 are identical output channels. The output buffers in this channel are compatible with various signaling standards – LP-HCSL and LVDS-like.

The LP-HCSL output buffer can be directly connected to the receiver without any termination resistor to GND. The output impedance of LP-HCSL is trimmed to 50 Ω ± 10%. A series resistor can be used to adapt to the trace impedance.
The LVDS-like requires a differential termination connected between the positive and negative polarity output pins. The termination can be connected directly or through an AC-coupling capacitor. For a 50-Ω system, a 100-Ω differential termination is appropriate.
LVCMOS outputs are designed for capacitive loads only. The polarity of the positive and negative output pins can be configured individually.

The differential buffers support wide range of output frequencies up to 328.125 MHz. LVCMOS supports up to 200 MHz.

Table 9-9 Configuring Input Reference/PFD/PLL Clock to Output ⁽⁷⁾

REGISTER BIT ADDRESS	REGISTER BIT FIELD NAME	DESCRIPTION
R25[10]	IP_BYP_OUT0_EN	Enables Reference Clock/PFD Clock to OUT0.
R25[9]	REF_CH_MUX	Selects between PFD Clock or Input Reference Clock
R25[14:11]	IP_REF_TO_OUT4_EN, IP_REF_TO_OUT3_EN, IP_REF_TO_OUT2_EN, IP_REF_TO_OUT1_EN	Selects reference clock to OUT1-OUT4
R56[15:14]	CH1_MUX	Clock selection MUX control for OUT1
R62[15:14]	CH2_MUX	Clock selection MUX control for OUT2
R67[15:14]	CH3_MUX	Clock selection MUX control for OUT3
R72[15:14]	CH4_MUX	Clock selection MUX control for OUT4

Table 9-10 Configuring Clock Distribution Network

REGISTER BIT ADDRESS	REGISTER BIT FIELD NAME	DESCRIPTION
R47[6:5]	PLL_PSB	Programmable Pre-scalar divider PSB
R47[4:3]	PLL_PSA	Programmable Pre-scalar divider PSA
R56[13:0]	CH1_DIV	OUT1 Integer Divider value
R62[13:0]	CH2_DIV	OUT2 Integer Divider value
R67[13:0]	CH3_DIV	OUT3 Integer Divider value
R72[13:0]	CH4_DIV	OUT4 Integer Divider value

Table 9-11 Configuring LVCMOS Output Buffer ⁽⁸⁾⁽⁹⁾

REGISTER BIT ADDRESS	REGISTER BIT FIELD NAME	DESCRIPTION
R78[12]	CH0_EN	Enables OUT0 LVCMOS Buffer
R79[3:0]	CH0_CMOS_SLEW_RATE_CTRL	Controls output slew rate of OUT0 LVCMOS Buffer
R59[14], R75[14]	CH1_CMOSN_EN, CH4_CMOSP_EN	Enables OUT1N/OUT4P LVCMOS Buffer
R59[13], R75[13]	CH1_CMOSP_EN, CH4_CMOSN_EN	Enables OUT1P/OUT4N LVCMOS Buffer
R59[12], R75[12]	CH1_CMOSN_POL, CH4_CMOSP_POL	Sets output polarity of OUT1N/OUT4P LVCMOS Buffer
R59[11], R75[11]	CH1_CMOSP_POL, CH4_CMOSN_POL	Sets output polarity of OUT1P/OUT4N LVCMOS Buffer
R60[3:0], R76[3:0]	CH1_CMOS_SLEW_RATE_CTRL, CH4_CMOS_SLEW_RATE_CTRL	Controls output slew rate of OUT1/OUT4 LVCMOS Buffer

Table 9-12 Configuring LP-HCSL Output Buffer ⁽¹⁰⁾⁽¹¹⁾⁽¹²⁾

REGISTER BIT ADDRESS	REGISTER BIT FIELD NAME	DESCRIPTION
R57[14] , R63[13], R68[13], R73[13]	CH1_HCSL_EN, CH2_HCSL_EN, CH3_HCSL_EN, CH4_HCSL_EN	Enables LP-HCSL buffer on OUT1/OUT2/OUT3/OUT4

Table 9-13 Configuring LVDS-Like Output Buffer ⁽¹³⁾⁽¹⁴⁾⁽¹⁵⁾

REGISTER BIT ADDRESS	REGISTER BIT FIELD NAME	DESCRIPTION
R59[15], R65[11], R70[11], R75[15]	CH1_LVDS_EN, CH2_LVDS_EN, CH3_LVDS_EN, CH4_LVDS_EN	Enables LVDS-like buffer on OUT1/OUT2/OUT3/OUT4
R60[15:12], R66[3:0], R71[3:0], R76[9:6]	CH1_DIFFBUF_IBIAS_TRIM, CH2_DIFFBUF_IBIAS_TRIM, CH3_DIFFBUF_IBIAS_TRIM, CH4_DIFFBUF_IBIAS_TRIM	Sets the output swing and output common mode of OUT1/OUT2/OUT3/OUT4
R60[11:10], R66[5:4], R71[5:4], R76[5:4]	CH1_LVDS_CMTRIM_INC, CH2_LVDS_CMTRIM_INC, CH3_LVDS_CMTRIM_INC, CH4_LVDS_CMTRIM_INC	Increases the output common mode of OUT1/OUT2/OUT3/OUT4. 2.5 V/3.3 V mode only.
R60[5:4], R65[14:13], R71[10:9], R77[1:0]	CH1_LVDS_CMTRIM_DEC, CH2_LVDS_CMTRIM_DEC, CH3_LVDS_CMTRIM_DEC, CH4_LVDS_CMTRIM_DEC	Decreases the output common mode of OUT1/OUT2/OUT3/OUT4. 2.5 V/3.3 V mode only.

7. It is recommended to disable any clock when not in use to reduce crosstalk

8. Multiple output buffers should not be enabled at the same time

9. Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V, safety_1p8v_mode should be set.

10. Multiple output buffers should not be enabled at the same time

11. External termination not needed. Voltage mode driver.

12. Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V, safety_1p8v_mode should be set.

13. Multiple output buffers should not be enabled at the same time.

14. 100 Ω differential termination needed in DC-coupled mode. 50 Ω single ended or 100 Ω differential termination needed in AC-coupled mode

15. Based on the VDDO levels, ch1_1p8vdet, ch2_1p8vdet, ch3_1p8vdet, ch4_1p8vdet should be set accordingly. When setting for 1.8V, safety_1p8v_mode should be set.