SNAS811 July   2020  – May  CDCE6214

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Application Example CDCE6214
  4. 4 Revision History
  5. 5 Description (cont.)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions G = Ground, P = Power I = Input, I/O = Input/Output, O = Output I, RPUPD = Input with Resistive Pull-up and Pull-down I, RPU = Input with Resistive Pull=up I/O, RPU = Input/Output with resistive pull-up
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  EEPROM Characteristics
    6. 7.6  Reference Input, Single-Ended Characteristics
    7. 7.7  Reference Input, Differential Characteristics
    8. 7.8  Reference Input, Crystal Mode Characteristics
    9. 7.9  General-Purpose Input Characteristics
    10. 7.10 Triple Level Input Characteristics
    11. 7.11 Logic Output Characteristics
    12. 7.12 Phase Locked Loop Characteristics
    13. 7.13 Closed-Loop Output Jitter Characteristics
    14. 7.14 Input and Output Isolation
    15. 7.15 Buffer Mode Characteristics
    16. 7.16 PCIe Spread Spectrum Generator
    17. 7.17 LVCMOS Output Characteristics
    18. 7.18 LP-HCSL Output Characteristics
    19. 7.19 LVDS Output Characteristics
    20. 7.20 Output Synchronization Characteristics
    21. 7.21 Power-On Reset Characteristics
    22. 7.22 I2C-Compatible Serial Interface Characteristics
    23. 7.23 Timing Requirements, I2C-Compatible Serial Interface
    24. 7.24 Power Supply Characteristics
    25. 7.25 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Reference Inputs
    2. 8.2 Outputs
    3. 8.3 Serial Interface
    4. 8.4 PSNR Test
    5. 8.5 Clock Interfacing and Termination
      1. 8.5.1 Reference Input
      2. 8.5.2 Outputs
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Reference Block
        1. 9.3.1.1 Zero Delay Mode, Internal and External Path
      2. 9.3.2 Phase-Locked Loop (PLL)
        1. 9.3.2.1 PLL Configuration and Divider Settings
        2. 9.3.2.2 Spread Spectrum Clocking
        3. 9.3.2.3 Digitally-Controlled Oscillator/ Frequency Increment and Decrement - Serial Interface Mode and GPIO Mode
      3. 9.3.3 Clock Distribution
        1. 9.3.3.1 Glitchless Operation
        2. 9.3.3.2 Divider Synchronization
        3. 9.3.3.3 Global and Individual Output Enable
      4. 9.3.4 Power Supplies and Power Management
      5. 9.3.5 Control Pins
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation Modes
        1. 9.4.1.1 Fall-Back Mode
        2. 9.4.1.2 Pin Mode
        3. 9.4.1.3 Serial Interface Mode
    5. 9.5 Programming
      1. 9.5.1 I2C Serial Interface
      2. 9.5.2 EEPROM
        1. 9.5.2.1 EEPROM - Cyclic Redundancy Check
        2. 9.5.2.2 Recommended Programming Procedure
        3. 9.5.2.3 EEPROM Access
          1. 9.5.2.3.1 Register Commit Flow
          2. 9.5.2.3.2 Direct Access Flow
        4. 9.5.2.4 Register Bits to EEPROM Mapping
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 Power-Up Sequence
    2. 11.2 Decoupling
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
      2. 13.1.2 Device Nomenclature
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

9.3.2 Phase-Locked Loop (PLL)

The CDCE6214 has a fully-integrated Phase-Locked Loop (PLL) circuit. The error between a reference phase and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an internal Voltage-Controlled Oscillator (VCO). The frequency of the VCO is fed through a feedback divider (N-counter) back to the PFD.

  • Integer and Fractional-N PLL mode of operation.
  • First-, Second-, or Third-Order MASH operation in Fractional mode.
  • 24-bit Numerator and Denominator can be used to generate fractional frequencies with 0 ppb frequency accuracy.
  • PFD operates between 1 MHz and 100 MHz.
  • Live Lock Detector (R7[0] or PLL_LOCK in GPIO) provides PLL Lock status (in fractional mode and SSC enabled, lock detect window need to be widened. R50[10:8] = 7h). Additionally, sticky bit lock detect (R7[1]) detects if there was any temporary loss of lock.
  • Integrated selectable loop filter components.
  • For a 25-MHz PFD frequency, PFD bandwidth between 100 kHz and 1.6 MHz can be achieved to optimize PLL to input reference.
  • Voltage-controlled oscillator (VCO) ranges from 2335 MHz to 2615 MHz.
  • Supports 0.25% and 0.5% center and down spread Spread Spectrum Clocking (SSC) generation. Further, VCO also supports up to 0.5% SSC references at 100 MHz for PCIe clocking.

Table 3. Common Clock Generator Loop Filter Settings

fVCO IN MHz fPFD IN MHz BW IN MHz PHASE MARGIN IN ° DAMPING FACTOR ICP IN mA CPcap IN pF RRes IN kΩ CZcap IN pF
2400 25 0.469 70 0.5 0.60 16.1 2.5 580
2400 50 0.938 70 2 0.60 8.2 2.5 276
2400 100 1.60 70 0.5 0.80 8.2 2.5 303
2457.6 61.44 1.04 70 1.15 0.60 9.2 2.0 331
2500 25 0.49 70 0.4 0.60 13.5 2.5 497
2500 50 0.93 70 1.0 0.60 11.7 2.5 386
2400 50 400 65 0.1 0.40 11.7 1.5 636

Table 4. Common PLL Divider Settings (4)

INPUT FREQUENCY IN MHz fPFD IN MHz OUTPUT FREQUENCY IN MHz fVCO N-COUNTER DIVIDER VALUE NUMERATOR DENOMINATOR PSA OUTPUT DIVIDER
25 50 100 2400 48 NA NA 4 6
25 25 100 2400 96 NA NA 4 6
25 50 156.25 2500 50 NA NA 4 4
25 25 25 2400 96 NA NA 4 24
25 25 24.576 2457.6 98 5071614 16682942 4 25
25 25 148.5 2376 95 664983 16624579 4 4
4. Fractional Mode settings are based on DCO mode step size of 0.1ppm
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