ZHCSTF3I June 2007 – August 2024 CDCE913 , CDCEL913
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 EEPROM Specification
- 5.7 Timing Requirements: CLK_IN
- 5.8 Timing Requirements: SDA/SCL #GUID-DE171716-D3A0-4375-A25C-58C636304087/SCAS849414
- 5.9 Typical Characteristics
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Register Maps
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
8.2.2.2 PLL Frequency Planning
At a given input frequency (ƒIN), use Equation 1 to calculate the output frequency (ƒOUT) of the CDCE913 or CDCEL913 device.
Equation 1. 
where
- M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL
- Pdiv (1 to 127) is the output divider
Use Equation 2 to calculate the target VCO frequency (ƒVCO) of each PLL.
Equation 2. 
The PLL internally operates as fractional divider and requires the following multiplier/divider settings:
- N
- P = 4 – int(log2N/M; if P < 0 then P = 0
- Q = int(N'/M)
- R = N′ – M × Q
where
N′ = N × 2P
N ≥ M;
80 MHz ≤ ƒVCO ≤ 230 MHz
16 ≤ Q ≤ 63
0 ≤ P ≤ 4
0 ≤ R ≤ 51
| Example: | |||
| for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2 | for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2 | ||
| → | fOUT = 54 MHz | → | fOUT = 74.25 MHz |
| → | fVCO = 108 MHz | → | fVCO = 148.50 MHz |
| → | P = 4 – int(log24) = 4 – 2 = 2 | → | P = 4 – int(log25.5) = 4 – 2 = 2 |
| → | N' = 4 × 22 = 16 | → | N' = 11 × 22 = 44 |
| → | Q = int(16) = 16 | → | Q = int(22) = 22 |
| → | R = 16 – 16 = 0 | → | R = 44 – 44 = 0 |
The values for P, Q, R, and N’ are automatically calculated when using TI Pro-Clock™ software.