ZHCSTF3I June 2007 – August 2024 CDCE913 , CDCEL913
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 EEPROM Specification
- 5.7 Timing Requirements: CLK_IN
- 5.8 Timing Requirements: SDA/SCL #GUID-DE171716-D3A0-4375-A25C-58C636304087/SCAS849414
- 5.9 Typical Characteristics
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Application and Implementation
- 9 Register Maps
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
7.4.1 SDA/SCL Hardware Interface
Figure 7-2 shows how the CDCE913 or CDCEL913 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple devices can be connected to the bus, but reducing the speed (400 kHz is the maximum) can be necessary if many devices are connected.
Note that the pullup resistors (RP) depend on the supply voltage, bus capacitance, and number of connected devices. The recommended pullup value is 4.7 kΩ. The pullup value must meet the minimum sink current of 3 mA at VOLmax = 0.4 V for the output stages (for more details see the SMBus or I2C Bus specification).
Figure 7-2 SDA / SCL Hardware Interface