9.3.1 Control Terminal Setting

The CDCEx925 has three user-definable control terminals (S0, S1, and S2) which allow external control of device settings. They can be programmed to any of the following settings:

• Spread spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

SDA/S1 and SCL/S2 pins of the CDCEx925 are dual-function pins. In the default configuration, they are predefined as the SDA/SCL serial programming interface. They can be programmed to control pins (S1/S2) by setting the relevant bits in the EEPROM. Note that the changes of the bits in the control register (bit [6] of byte 02h) have no effect until they are written into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if V_DDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin; it is a control pin only.

9.3.2 Default Device Setting

The internal EEPROM of CDCEx925 is preconfigured as shown in Figure 7. The input frequency is passed through the output as a default. This allows the device to operate in default mode without the extra production step of programming it. The default setting appears after power is supplied or after a power-down/up sequence until it is reprogrammed by the user to a different application configuration. A new register setting is programmed through the serial SDA/SCL interface.

Figure 7. Preconfiguration of CDCEx925 Internal EEPROM

Table 4 shows the factory default setting for the control terminal register (external control pins). Note that even though eight different register settings are possible, in default configuration, only the first two settings (0 and 1) can be selected with S0, as S1 and S2 are configured as programming pins in the default mode.

9.3.3 SDA/SCL Serial Interface

This section describes the SDA/SCL interface of the CDCEx925 device. The CDCEx925 operates as a slave device of the 2-wire serial SDA/SCL bus, compatible with the popular SMBus or I²C specification. It operates in the standard-mode transfer (up to 100 kbps) and fast-mode transfer (up to 400 kbps) and supports 7-bit addressing.

The SDA/S1 and SCL/S2 pins of the CDCEx925 are dual-function pins. In the default configuration they are used as SDA/SCL serial programming interface. They can be reprogrammed as general-purpose control pins, S1 and S2, by changing the corresponding EEPROM setting, byte 02h, bit [6].

Figure 8. Timing Diagram for SDA/SCL Serial Control Interface

9.3.4 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with most-significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of bytes read out are defined by byte count in the generic configuration register. At the Block Read instruction, all bytes defined in the byte count must be read out to finish the read cycle correctly.

Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to each transferred byte regardless of whether this is a Byte Write or a Block Write sequence.

If the EEPROM write cycle is initiated, the internal SDA registers are written into the EEPROM. During this write cycle, data is not accepted at the SDA/SCL bus until the write cycle is completed. However, data can be read out during the programming sequence (Byte Read or Block Read). The programming status can be monitored by EEPIP, byte 01h–bit 6.

The offset of the indexed byte is encoded in the command code, as described in Table 5.

9.4.1 SDA/SCL Hardware Interface

Figure 9 shows how the CDCEx925 clock synthesizer is connected to the SDA/SCL serial interface bus. Multiple devices can be connected to the bus, but the speed may need to be reduced (400 kHz is the maximum) if many devices are connected.

Note that the pullup resistors (R_P) depend on the supply voltage, bus capacitance, and number of connected devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at V_OLmax = 0.4 V for the output stages (for more details, see SMBus or I²C Bus specification).

Figure 9. SDA/SCL Hardware Interface

Table 6. Command Code Definition

9.6.1 SDA/SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and explanations describe the programmable functions of the CDCEx925. All settings can be manually written into the device through the SDA/SCL bus or easily programmed by using the TI Pro-Clock™ software. TI Pro-Clock software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter.

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2 (see Control Terminal Setting).

Table 9. Generic Configuration Register

OFFSET(1)	BIT(2)	ACRONYM	DEFAULT(3)	DESCRIPTION
00h	7	E_EL	Xb	Device identification (read-only): 1 is CDCE925 (3.3 V out), 0 is CDCEL925 (1.8 V out)
	6:4	RID	Xb	Revision identification number (read-only)
	3:0	VID	1h	Vendor identification number (read-only)
01h	7	–	0b	Reserved – always write 0
	6	EEPIP	0b	EEPROM programming Status4:(4) (read-only)			0 – EEPROM programming is completed 1 – EEPROM is in programming mode
	5	EELOCK	0b	Permanently lock EEPROM data(5)			0 – EEPROM is not locked 1 – EEPROM is permanently locked
	4	PWDN	0b	Device power down (overwrites S0/S1/S2 setting; configuration register settings are unchanged) Note: PWDN cannot be set to 1 in the EEPROM. 0 – Device active (all PLLs and all outputs are enabled) 1 – Device power down (all PLLs in power down and all outputs in high-impedance state)
	3:2	INCLK	00b	Input clock selection:		00 – Xtal  01 – VCXO   10 – LVCMOS 1 – Reserved
	1:0	SLAVE_ADR	00b	Address bits A0 and A1 of the slave receiver address
02h	7	M1	1b	Clock source selection for output Y1:			0 – Input clock  1 – PLL1 clock
	6	SPICON	0b	Operation mode selection for pins 14/15(6) 0 – Serial programming interface SDA (pin 15) and SCL (pin 14) 1 – Control pins S1 (pin 15) and S2 (pin 14)
	5:4	Y1_ST1	11b	Y1-State0/1 definition00 – Device power down (all PLLs in power down and all outputs in high-impedance state) 01 – Y1 disabled to high-impedance state 10 – Y1 disabled to low 11 – Y1 enabled
	3:2	Y1_ST0	01b
	1:0	Pdiv1 [9:8]	001h	10-bit Y1-Output-Divider Pdiv1:			0 – Divider is reset and in standby 1 to 1023 – Divider value
03h	7:0	Pdiv1 [7:0]
04h	7	Y1_7	0b	Y1_ST0/Y1_ST1 State Selection(7)
	6	Y1_6	0b		0 – State0 (predefined by Y1_ST0) 1 – State1 (predefined by Y1_ST1)
	5	Y1_6	0b
	4	Y1_6	0b
	3	Y1_6	0b
	2	Y1_6	0b
	1	Y1_6	0b
	0	Y1_6	0b
05h	7:3	XCSEL	0Ah	Crystal load-capacitor selection(8)		00h – 0 pF 01h – 1 pF 02h – 2 pF   : 14h to 1Fh – 20 pF
	2:0		0b	Reserved – do not write other than 0.
06h	7:1	BCOUNT	30h	7-bit byte count (defines the number of bytes which is sent from this device at the next Block Read transfer); all bytes must be read out to correctly finish the read cycle.
	0	EEWRITE	0b	Initiate EEPROM write cycle(9)		0 – No EEPROM write cycle 1 – Start EEPROM write cycle (internal registers are saved to the EEPROM)
07h-0Fh		—	0h	Reserved – do not write other than 0

(1) Writing data beyond 30h may affect device function.

(2) All data transferred with the MSB first

(3) Unless customer-specific setting

(4) During EEPROM programming, no data is allowed to be sent to the device through the SDA/SCL bus until the programming sequence is completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).

(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. No further programming is possible. Data, however can still be written through the SDA/SCL bus to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only if written into the EEPROM.

(6) Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if V_DDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.

(7) These are the bits of the control terminal register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2.

(8) The internal load capacitor (C1, C2) must be used to achieve the best clock performance. External capacitors must be used only to finely adjust C_L by a few picofarads. The value of C_L can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For CL > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which always adds 1.5 pF (6 pF/2 pF) to the selected C_L. For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

(9) Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level-high does not trigger an EEPROM WRITE cycle. The EEWRITE bit must be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.