ZHCSTF3I June   2007  – August 2024 CDCE913 , CDCEL913

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 EEPROM Specification
    7. 5.7 Timing Requirements: CLK_IN
    8. 5.8 Timing Requirements: SDA/SCL #GUID-DE171716-D3A0-4375-A25C-58C636304087/SCAS849414
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Control Terminal Configuration
      2. 7.3.2 Default Device Configuration
      3. 7.3.3 SDA/SCL Serial Interface
      4. 7.3.4 Data Protocol
    4. 7.4 Device Functional Modes
      1. 7.4.1 SDA/SCL Hardware Interface
    5. 7.5 Programming
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Spread-Spectrum Clock (SSC)
        2. 8.2.2.2 PLL Frequency Planning
        3. 8.2.2.3 Crystal Oscillator Start-up
        4. 8.2.2.4 Frequency Adjustment with Crystal Oscillator Pulling
        5. 8.2.2.5 Unused Inputs/Outputs
        6. 8.2.2.6 Switching Between XO and VCXO Mode
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Register Maps
    1. 9.1 SDA/SCL Configuration Registers
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 Trademarks
    5. 10.5 静电放电警告
    6. 10.6 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

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7.3.2 Default Device Configuration

The internal EEPROM of the CDCE913 or CDCEL913 is preconfigured with a factory default configuration, as shown in Figure 7-1 (The input frequency is passed through the output as a default). This preconfiguration allows the device to operate in default mode without the extra production step of programming. The default setting appears after power is supplied or after a power-down–power-up sequence, until the device is reprogrammed by the user to a different application configuration. A new register setting is programmed through the serial SDA/SCL interface.

CDCE913 CDCEL913 Default ConfigurationFigure 7-1 Default Configuration

Table 7-6 shows the factory default setting for the Control Terminal register. Though eight different register settings are possible, in the default configuration, only the first two settings (0 and 1) can be selected with S0, as S1 and S2 are configured as programming pins in default mode.

Table 7-6 Factory Default Setting for Control Terminal Register(1)
Y1PLL1 SETTINGS
EXTERNAL CONTROL PINSOUTPUT
SELECTION		FREQUENCY
SELECTION		SSC
SELECTION		OUTPUT
SELECTION
S2S1S0Y1FS1SSC1Y2Y3
SCL (I2C)SDA (I2C)03-statefVCO1_0off3-state
SCL (I2C)SDA (I2C)1EnabledfVCO1_0offEnabled
(1) In default mode or when programmed respectively, S1 and S2 act as serial programming interface, SDA/SCL. S1 and S2 do not have any control-pin function but are internally interpreted as if S1 = 0 and S2 = 0. S0, however, is a control pin, which in the default mode switches all outputs ON or OFF (as previously predefined).
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