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ZHCSTF3I June 2007 – August 2024 CDCE913 , CDCEL913

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机械数据 (封装 | 引脚)

PW|14
- MPDS360A

散热焊盘机械数据 (封装 | 引脚)

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7.3.1 Control Terminal Configuration

The CDCE913 or CDCEL913 has three user-definable control terminals (S0, S1, and S2), which allow external control of device settings. The devices can be programmed to any of the following functions:

Spread-spectrum clocking selection → spread type and spread amount selection
Frequency selection → switching between any of two user-defined frequencies
Output state selection → output configuration and power-down control

The user can predefine up to eight different control settings. Table 7-1 and Table 7-2 explain these settings.

Table 7-1 Control Terminal Definition

EXTERNAL CONTROL BITS	PLL1 SETTING			Y1 SETTING
Control function	PLL frequency selection	SSC selection	Output Y2/Y3 selection	Output Y1 and power-down selection

Table 7-2 PLLx Setting (Can Be Selected for Each PLL Individually)⁽¹⁾

SSCx [3 Bits]			CENTER	DOWN
SSC SELECTION (CENTER/DOWN)
0	0	0	0% (off)	0% (off)
0	0	1	±0.25%	–0.25%
0	1	0	±0.5%	–0.5%
0	1	1	±0.75%	–0.75%
1	0	0	±1.0%	–1.0%
1	0	1	±1.25%	–1.25%
1	1	0	±1.5%	–1.5%
1	1	1	±2.0%	–2.0%

(1) Center-spread/down-spread, Frequency0/Frequency1 and State0/State1 are user-definable in PLLx configuration register.

Table 7-3 PLLx Setting, Frequency Selection (Can Be Selected for Each PLL Individually)⁽¹⁾

FSx	FUNCTION
0	Frequency0
1	Frequency1

(1) Frequency0 and Frequency1 can be any frequency within the specified f_VCO range.

Table 7-4 PLLx Setting, Output Selection⁽¹⁾ (Y2 ... Y3)

YxYx	FUNCTION
0	State0
1	State1

(1) State0/State1 selection is valid for both outputs of the corresponding PLL module and can be power down, 3-state, low, or active.

Table 7-5 Y1 Setting⁽¹⁾

Y1 SELECTION
Y1	FUNCTION
0	State 0
1	State 1

(1) State0 and State1 are user definable in the generic configuration register and can be power down, 3-state, low, or active.

S1/SDA and S2/SCL pins of the CDCE913 or CDCEL913 are dual-function pins. In the default configuration, the pins are defined as SDA/SCL for the serial programming interface. The pins can be programmed as control pins (S1/S2) by setting the appropriate bits in the EEPROM. Changes to the control register (Bit [6] of byte 02h) have no effect until the pins are written into the EEPROM.

After the S1/SDA and S2/SCL pins are set as control pins, the serial programming interface is no longer available. However, if V_DDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA/SCL).

S0 is not a multi-use pin. S0 is a control pin only.