10.3.1 Control Terminal Setting

The CDCEx937-Q1 has three user-definable control terminals (S0, S1, and S2) that allow external control of device settings. They can be programmed to any of the following setting:

• Spread spectrum clocking selection → spread type and spread amount selection
• Frequency selection → switching between any of two user-defined frequencies
• Output state selection → output configuration and power down control

The user can predefine up to eight different control settings. Table 1 and Table 2 explain these settings.

S1/SDA and S2/SCL pins of the CDCEx937-Q1 are dual function pins. In default configuration they are defined as SDA and SCL for the serial interface. They can be programmed as control-pins (S1/S2) by setting the relevant bits in the EEPROM. Note that the changes to the Control register (Bit [6] of Byte [02]) have no effect until they are written into the EEPROM.

Once they are set as control pins, the serial programming interface is no longer available. However, if V_DDOUT is forced to GND, the two control-pins, S1 and S2, temporally act as serial programming pins (SDA and SCL).

S0 is not a multi-use pin, it is a control pin only.

10.3.2 Default Device Setting

The internal EEPROM of CDCEx937-Q1 is preconfigured as shown in Figure 6. The input frequency is passed through to the output as a default. This allows the device to operate in default mode without the extra production step of program it. The default setting appears after power is supplied or after power-down or power-up sequence until it is re-programmed by the user to a different application configuration. A new register setting is programmed through the serial SDA and SCL interface.

Figure 6. Default Device Setting

Table 4 shows the factory default setting for the Control Terminal Register (external control pins). In normal operation, all 8 register settings are available, but in the default configuration only the first two settings (0 and 1) can be selected with S0, as S1 and S2 configured as programming pins in default mode.

10.4.1 SDA and SCL Serial Interface

The CDCEx937-Q1 operates as a slave device of the 2-wire serial SDA and SCL bus, compatible with the popular SMBus or I²C specification. It operates in the standard-mode transfer (up to 100kbit/s) and fast-mode transfer (up to 400kbit/s) and supports 7-bit addressing.

The S1/SDA and S2/SCL pins of the CDC9xx are dual function pins. In the default configuration they are used as SDA and SCL serial programming interface. They can be re-programmed as general purpose control pins, S1 and S2, by changing the corresponding EEPROM setting, Byte 02, Bit [6].

10.5.1 Data Protocol

The device supports Byte Write and Byte Read and Block Write and Block Read operations.

For Byte Write/Read operations, the system controller can individually access addressed bytes.

For Block Write/Read operations, the bytes are accessed in sequential order from lowest to highest byte (with most significant bit first) with the ability to stop after any complete byte has been transferred. The numbers of Bytes read-out are defined by Byte Count in the Generic Configuration Register. At Block Read instruction all bytes defined in the Byte Count has to be readout to correctly finish the read cycle.

Once a byte has been sent, it is written into the internal register and is effective immediately. This applies to each transferred byte independent of whether this is a Byte Write or a Block Write sequence.

If the EEPROM Write Cycle is initiated, the internal SDA register contents are written into the EEPROM. During this write cycle, data is not accepted at the SDA and SCL bus until the write cycle is completed. However, data can be read during the programming sequence (Byte Read or Block Read). The programming status can be monitored by reading EEPIP, Byte 01–Bit [6].

The offset of the indexed byte is encoded in the command code, as described in Table 5.

10.5.2 Command Code Definition

10.5.3 Generic Programming Sequence

Figure 7. Generic Programming Sequence

10.5.4 Byte Write Programming Sequence

Figure 8. Byte Write Protocol

10.5.5 Byte Read Programming Sequence

Figure 9. Byte Read Protocol

10.5.6 Block Write Programming Sequence1

1. Data byte 0 bits [7:0] is reserved for Revision Code and Vendor Identification. Also, it is used for internal test purpose and must not be overwritten.

Figure 10. Block Write Protocol

10.5.7 Block Read Programming Sequence

Figure 11. Block Read Protocol

10.5.8 Timing Diagram for the SDA and SCL Serial Control Interface

Figure 12. Timing Diagram for SDA and SCL Serial Control Interface

10.5.9 SDA and SCL Hardware Interface

Figure 13 shows how the CDCEx937-Q1 clock synthesizer is connected to the SDA and SCL serial interface bus. Multiple devices can be connected to the bus but the speed may require reduction if many devices are connected (400 kHz is the maximum).

Note that the pullup resistors (R_P) depends on the supply voltage, bus capacitance, and number of connected devices. The recommended pullup value is 4.7 kΩ. It must meet the minimum sink current of 3 mA at V_OLmax = 0.4 V for the output stages (for more details see SMBus or I²C Bus specification).

Figure 13. SDA and SCL Hardware Interface

10.6.1 SDA and SCL Configuration Registers

The clock input, control pins, PLLs, and output stages are user configurable. The following tables and explanations describe the programmable functions of the CDCEx937-Q1. All settings can be manually written into the device through the SDA and SCL bus or easily programmed by using the TI Pro-Clock software. TI Pro-Clock software allows the user to quickly make all settings and automatically calculates the values for optimized performance at lowest jitter.

The grey-highlighted bits, described in the Configuration Registers tables in the following pages, belong to the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2 (see the Control Terminal Configuration section).

Table 9. Generic Configuration Register

OFFSET(1)	BIT(2)	ACRONYM	DEFAULT(3)	DESCRIPTION
00h	7	E_EL	Xb	Device identification (read-only): 1 is CDCE937-Q1 (3.3 V), 0 is CDCEL937-Q1 (1.8 V)
	6:4	RID	Xb	Revision Identification Number (read only)
	3:0	VID	1h	Vendor Identification Number (read only)
01h	7	–	0b	Reserved – always write 0
	6	EEPIP	0b	EEPROM Programming Status:(4) (read only)			0 – EEPROM programming is completed 1 – EEPROM is in programming mode
	5	EELOCK	0b	Permanently Lock EEPROM Data(5)			0 – EEPROM is not locked 1 – EEPROM is permanently locked
	4	PWDN	0b	Device Power Down (overwrites S0/S1/S2 setting; configuration register settings are unchanged) Note: PWDN cannot be set to 1 in the EEPROM.
					0 – device active (PLL1 and all outputs are enabled) 1 – device power down (PLL1 in power down and all outputs in 3-state)
	3:2	INCLK	00b	Input clock selection:		00 – Xtal  01 – VCXO   10 – LVCMOS  11 – reserved
	1:0	SLAVE_ADR	01b	Programmable Address Bits A0 and A1 of the Slave Receiver Address
02h	7	M1	1b	Clock source selection for output Y1:			0 – input clock  1 – PLL1 clock
	6	SPICON	0b	Operation mode selection for pin 18/19(6)
					0 – serial programming interface SDA (pin 19) and SCL (pin 18) 1 – control pins S1 (pin 19) and S2 (pin 18)
	5:4	Y1_ST1	11b	Y1-State0/1 Definition
	3:2	Y1_ST0	01b		00 – device power down (all PLLs in power down and all outputs in 3-State) 01 – Y1 disabled to 3-state			10 – Y1 disabled to low 11 – Y1 enabled
	1:0	Pdiv1 [9:8]	001h	10-Bit Y1-Output-Divider Pdiv1:			0 – divider reset and stand-by 1-to-1023 – divider value
03h	7:0	Pdiv1 [7:0]
04h	7	Y1_7	0b	Y1_ST0/Y1_ST1 State Selection(7)
	6	Y1_6	0b		0 – State0 (predefined by Y1_ST0) 1 – State1 (predefined by Y1_ST1)
	5	Y1_5	0b
	4	Y1_4	0b
	3	Y1_3	0b
	2	Y1_2	0b
	1	Y1_1	1b
	0	Y1_0	0b
05h	7:3	XCSEL	0Ah	Crystal Load Capacitor Selection(8)		00h → 0 pF 01h → 1 pF 02h → 2 pF   : 14h-to-1Fh → 20 pF
	2:0		0b	Reserved – do not write other than 0
06h	7:1	BCOUNT	40h	7-Bit Byte Count (defines the number of bytes which is sent from this device at the next Block Read transfer); all bytes have to be read out to correctly finish the read cycle.)
	0	EEWRITE	0b	Initiate EEPROM Write Cycle(4) (9)		0– no EEPROM write cycle 1 – start EEPROM write cycle (internal configuration register is saved to the EEPROM)
07h-0Fh		—	0h	Unused address range

(1) Writing data beyond ‘40h’ may affect device function.

(2) All data transferred with the MSB first.

(3) Unless customer-specific setting.

(4) During EEPROM programming, no data is allowed to be sent to the device through the SDA and SCL bus until the programming sequence is completed. Data, however, can be read out during the programming sequence (Byte Read or Block Read).

(5) If this bit is set to high in the EEPROM, the actual data in the EEPROM is permanently locked. There is no further programming possible. Data, however can still be written through SDA and SCL bus to the internal register to change device function on the fly. But new data can no longer be saved to the EEPROM. EELOCK is effective only, if written into the EEPROM!

(6) Selection of control pins is effective only if written into the EEPROM. Once written into the EEPROM, the serial programming pins are no longer available. However, if V_DDOUT is forced to GND, the two control pins, S1 and S2, temporally act as serial programming pins (SDA and SCL), and the two slave receiver address bits are reset to A0 = 0 and A1 = 0.

(7) These are the bits of the Control Terminal Register. The user can predefine up to eight different control settings. These settings then can be selected by the external control pins, S0, S1, and S2.

(8) The internal load capacitor (C1, C2) has to be used to achieve the best clock performance. External capacitors must be used only to finely adjust C_L by a few pF's. The value of C_L can be programmed with a resolution of 1 pF for a crystal load range of 0 pF to 20 pF. For C_L > 20 pF, use additional external capacitors. Also, the value of the device input capacitance has to be considered which always adds 1.5 pF (6 pF//2 pF) to the selected C_L. For more information about VCXO configuration and crystal recommendation, see VCXO Application Guideline for CDCE(L)9xx Family (SCAA085).

(9) Note: The EEPROM WRITE bit must be sent last. This ensures that the content of all internal registers are stored in the EEPROM. The EEWRITE cycle is initiated with the rising edge of the EEWRITE bit. A static level high does not trigger an EEPROM WRITE cycle. The EEWRITE bit has to be reset to low after the programming is completed. The programming status can be monitored by reading out EEPIP. If EELOCK is set to high, no EEPROM programming is possible.