SCAS892C
February 2010 – December 2016
CDCE937-Q1
,
CDCEL937-Q1
PRODUCTION DATA.
1
Features
2
Applications
3
Description
4
Revision History
5
Description (continued)
6
Device Comparison Table
7
Pin Configuration and Functions
8
Specifications
8.1
Absolute Maximum Ratings
8.2
ESD Ratings
8.3
Recommended Operating Conditions
8.4
Thermal Information
8.5
Electrical Characteristics
8.6
Timing Requirements
8.7
Typical Characteristics
9
Parameter Measurement Information
10
Detailed Description
10.1
Overview
10.2
Functional Block Diagram
10.3
Feature Description
10.3.1
Control Terminal Setting
10.3.2
Default Device Setting
10.4
Device Functional Modes
10.4.1
SDA and SCL Serial Interface
10.5
Programming
10.5.1
Data Protocol
10.5.2
Command Code Definition
10.5.3
Generic Programming Sequence
10.5.4
Byte Write Programming Sequence
10.5.5
Byte Read Programming Sequence
10.5.6
Block Write Programming Sequence
10.5.7
Block Read Programming Sequence
10.5.8
Timing Diagram for the SDA and SCL Serial Control Interface
10.5.9
SDA and SCL Hardware Interface
10.6
Register Maps
10.6.1
SDA and SCL Configuration Registers
11
Application and Implementation
11.1
Application Information
11.2
Typical Application
11.2.1
Design Requirements
11.2.2
Detailed Design Procedure
11.2.2.1
Spread-Spectrum Clock (SSC)
11.2.2.2
PLL Multiplier or Divider Definition
11.2.2.3
Crystal Oscillator Start-Up
11.2.2.4
Frequency Adjustment With Crystal Oscillator Pulling
11.2.2.5
Unused Inputs and Outputs
11.2.2.6
Switching Between XO and VCXO Mode
11.2.3
Application Curves
12
Power Supply Recommendations
13
Layout
13.1
Layout Guidelines
13.2
Layout Example
14
Device and Documentation Support
14.1
Documentation Support
14.1.1
Related Documentation
14.2
Related Links
14.3
Receiving Notification of Documentation Updates
14.4
Community Resources
14.5
Trademarks
14.6
Electrostatic Discharge Caution
14.7
Glossary
15
Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
PW|20
MPDS362A
散热焊盘机械数据 (封装 | 引脚)
订购信息
scas892c_oa
scas892c_pm
9
Parameter Measurement Information
Figure 4.
Test Load
Figure 5.
Test Load for 50-Ω Board Environment
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