ZHCSGV7F July 2017 – January 2024 CDCI6214
PRODUCTION DATA
The ultra-low power clock generator is controlled by multiple LVCMOS input pins.
EEPROMSEL acts as EEPROM page select. The CDCI6214 clock generator contains two pages of configuration settings. The level of this pin is sampled after device power-up. A low level selects page zero. A high level selects page one. The EEPROMSEL pin is a tri-level input pin. This third voltage level is automatically applied by an internal voltage divider. The mid-level is used to select an internal default where the serial interface is enabled.
RESETN/SYNC (pin 8) , SCL (pin 12), and SDA (pin 19) have a secondary functionality and can act as general-purpose inputs and outputs (GPIO). This means that either the serial interface or the GPIO functionality can be active.
RESETN/SYNC resets the internal circuitry and is used in the initial power-up sequence. The pin can be reconfigured to act as synchronization input. The differential outputs are kept in mute while SYNC is low. When SYNC is high, outputs are active. Moreover status signals can be driven by this pin.
SCL can act as general-purpose input.
SDA can act as general-purpose input and output.
REFSEL is used to select between the input references to the PLL. A low level selects the crystal reference on XIN. A high level selects the differential input reference on REFP, REFN.
| PIN | RECONFIGURABLE? | INPUT | OUTPUT | TERMINATION | ||||
|---|---|---|---|---|---|---|---|---|
| NO. | NAME | GPIO | 2-LOGIC-LEVELS | 3-LOGIC-LEVELS | 2-LEVEL | PULLDOWN | PULLUP | |
| 23 | EEPROMSEL | - | – | – | yes | – | 50 kΩ | 50 kΩ |
| 20 | STATUS | GPIO1 | yes | yes | – | yes | – | 50 kΩ |
| 19 | SDA | GPIO2 | yes | yes | – | yes | – | – |
| 12 | SCL | GPIO3 | yes | yes | – | – | – | – |
| 11 | OE | GPIO4 | yes | yes | – | yes | – | 50 kΩ |
| 8 | RESETN | GPIO0 | yes | yes | – | yes | – | 50 kΩ |
| 4 | REFSEL | - | – | – | yes | – | 50 kΩ | 50 kΩ |
| SIGNAL NO. (1) | ABBREVIATION | DESCRIPTION |
|---|---|---|
| 0 | FREQ_INC | Frequency increment; increments the IOD(2) |
| 1 | FREQ_DEC | Frequency decrement; decrements the IOD.(2) |
| 2 | OE (global) | Enables or disables all differential outputs Y[4:1] (bypass not affected).(3) |
| 4 | OE_Y1 | Enables or disables Y1. (3) |
| 5 | OE_Y2 | Enables or disables Y2. (3) |
| 6 | OE_Y3 | Enables or disables Y3. (3) |
| 7 | OE_Y4 | Enables or disables Y4. (3) |
GENERIC1.
| SIGNAL NO.(1) | ABBREVIATION | DESCRIPTION |
|---|---|---|
| 0 | PLL_LOCK | 0 = PLL out of lock; 1 = indicates PLL in lock |
| 1 | XTAL_OSC | 0 = crystal failure; 1 = crystal oscillates |
| 2 | CAL_DONE | 0 = PLL (VCO) calibration ongoing; 1 = calibration done |
| 3 | CONF_DONE | 0 = device logic busy; 1 = device operational |
| 4 | SYNC_DONE | 0 = output sync ongoing, muted; 1 = outputs released operational |
| 5 | EEPROM_BUSY | 0 = EEPROM idle; 1 = EEPROM access ongoing |
| 6 | EEPROM_Y12 | 0 = EEPROM pin sees low level; 1 = EEPROM pin sees high level |
| 7 | EEPROM_M12 | 0 = EEPROM pin sees low or high level; 1 = EEPROM pin sees mid level |
| 8 | I2C_LSB | Indicates I2C target address LSB config from loaded EEPROM |
| 9 | CLK_FSM | Clock, State machine |
| 10 | CLK_PFD_REF | Clock, PFD, reference |
| 11 | CLK_PFD_FB | Clock, PFD, feedback |
| 12 | BUF_SYNC | buffered SYNC pin |
| 13 | BUF_SCL | buffered SCL pin |
| 14 | BUF_SDA | buffered received SDA pin |