The CDCI6214 contains a fully integrated phase-locked loop circuit. The error between a reference phase and an internal feedback phase is compared at the phase-frequency-detector. The comparison result is fed to a charge pump that is connected to an integrated loop filter. The control voltage resulting from the loop filter tunes an internal voltage-controlled oscillator (VCO). The frequency of the VCO is fed through a pre-scaler feedback divider (PSFB) and another feedback divider back to the PFD.

The PLL closed-loop bandwidth is configurable using registers PLL0, PLL1, and PLL2.

• Integer PLL
• PFD operates 1 MHz to 100 MHz
• Live Lock-Detector provides PLL lock status on status pin and bit lock_det (there is an additional sticky bit unlock_s)
• Integrated selectable loop filter components
• For 25-MHz PFD bandwidths between 100 kHz and 3000 kHz can be achieved to optimize PLL to input reference
• Voltage-Controlled Oscillator (VCO) tuning range of 2400 to 2800 MHz
• VCO is compatible to 0.5% spread spectrum (SSC) references at 100 MHz.

Figure 8-3 Phase-Locked Loop Circuit