ZHCSD30 November   2014 CDCL1810A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 简化电路原理图
  5. 5 修订历史记录
  6. 6 Device Comparison Tables
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 Handling Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 DC Electrical Characteristics
    6. 8.6 AC Electrical Characteristics
    7. 8.7 AC Electrical Characteristics for the SDA/SCL Interface
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Output Enable/Disable
      2. 9.3.2 SDA/SCL Interface
        1. 9.3.2.1 SDA/SCL Bus Slave Device Address
        2. 9.3.2.2 SDA/SCL Connections Recommendations
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 SDA/SCL Interface
      2. 9.5.2 Command Code Definition
      3. 9.5.3 SDA/SCL Timing Characteristics
      4. 9.5.4 SDA/SCL Programming Sequence
    6. 9.6 Register Maps
      1. 9.6.1 SDA/SCL Bus Configuration Command Bitmap
        1. 9.6.1.1 Byte 0:
        2. 9.6.1.2 Byte 1:
        3. 9.6.1.3 Byte 2:
        4. 9.6.1.4 Byte 3:
        5. 9.6.1.5 Byte 4:
        6. 9.6.1.6 Byte 5:
        7. 9.6.1.7 Byte 6:
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Clock Distribution for Multiple TI Keystone DSPs
        1. 10.1.1.1 Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 商标
    2. 13.2 静电放电警告
    3. 13.3 术语表
  14. 14机械封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

6 Device Comparison Tables

Table 1. TA Device Comparison

TA PACKAGED DEVICES FEATURES
–40°C to +85°C CDCL1810ARGZT 48-pin VQFN (RGZ) Package,
small tape and reel
–40°C to +85°C CDCL1810ARGZR 48-pin VQFN (RGZ) Package,
tape and reel

Table 2. Device Feature Comparison

FEATURE CDCL1810 CDCL1810A
Divider Synchronization after power up and after each programming access. During Synchronization all outputs are disabled. Yes No
Output Group Phase Adjustment Yes No
Device Revision ID b’011’ b’100’
1:10 Clock Fanout Yes Yes
Outputs grouped into two divider banks Yes Yes
Individual Output enabled/disable with I2C Yes Yes
Continuous and independent operation of outputs which are not programmed, while configuring and programming other outputs. No Yes
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